I followed the pci compiler user guideline and used PCI HOST BRIDGE in my project. The only difference is that I connected the same PLL output clock to pci ip core and external pci device.
After using Altera-provided constraint files in my design, I compiled the design and programmed the targeted Altera device. Finally, I found that the pci read or write operation is not stable. I don’t know how to fix the problem. Maybe there is something wrong with the sdc file. Could you help me to modify the pci sdc file? The pci trace length table and pci compiler sdc file are attached. Thank you for your help.
