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Altera_Forum
Honored Contributor I
1,196 Views

How to set up PCIe Gen3 simulation

I've been having issues with this and I'm wondering if I've even set everything up correctly. 

 

I have a completed application core that I want to connect to the Arria 10 Avalon streaming hard IP for PCIe (endpoint) and run a simulation using the root port BFM. The documentation talks about copying one of the example designs from the Quartus installation directory and simulating that. However, it doesn't really explain how to replace the example application (the APPS component I presume) with my own application component and simulate that. 

 

I've taken the example design ep_g3x4.qsys, which is closest to my PCIe configuration, and customized the PCIe parameters to match my design's configuration. Now what do I do? Am I on the right path? 

 

Previously, I tried just running "Generate Testbench System" from the PCIe IP parameter editor and then editing the generated testbench file to instantiate my application core. Now I'm thinking that that may have been completely wrong. 

 

Any help would be greatly appreciated.
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3 Replies
Altera_Forum
Honored Contributor I
175 Views

Sounds like you are in correct direction you can use "Generate Test Bench System" or Generate HDL and from "Simulation" tab select Simulation Model language.. 

 

Here is the video on how to bring up simulation for Qsys system. 

 

https://www.youtube.com/watch?v=e0x5kmvt4f8 

 

Hope this helps. 

 

Best Regards, 

arslanusman2003 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
175 Views

The intention of the auto generated rootport testbench is the simulation the PCIe Hard IP by connecting to the APPS components, the testbench only covers the .qsys example design under <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>_ed/example_design/, it doesn't covers the simulation of whole design environment such as when users add in their own application components.

Altera_Forum
Honored Contributor I
175 Views

 

--- Quote Start ---  

The intention of the auto generated rootport testbench is the simulation the PCIe Hard IP by connecting to the APPS components, the testbench only covers the .qsys example design under <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>_ed/example_design/, it doesn't covers the simulation of whole design environment such as when users add in their own application components. 

--- Quote End ---  

 

 

Currently, even I'm in the phase of setting up simulation environment for my PCIe design for Arria 10 GX. 

Could you please tell me what tests the basic test bench for PCIe does and where can I find those test logic? This would help me tweak it to add my own pcie test cases.
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