FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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How to simulate the hard IP libraries in cadence


HI I have created a QSYS design containing nios processor, emif IP, PCIE, etc. Design got synthesized. Now I want to check the design in cadence for which I generated Atlera as well as hard IP libraries from the tool. I ran the ncsim script provided. It generated the libraries. Now I copied the cds.lib and libraries to my simulation run directory. But after running the command. It is not taking the libraries and asking for individual files. Is this the way we need to provide the individual files and create a filelist or just including the libraries will do. Please help.

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I will proceed with case closure as the user has found the solution.

I will describe the issue detail below for reference.

Description: The ncsim was run in 32 bit while the libraries were compiled in 64 bit. Thus, it is not compiling the libraries.

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