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How to use Nios ↔ Logic (Avalon mm Burst Transfer)

jjang
Beginner
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i wanna Burst Transfer or Steamming data communication Between Logic and NIOS.

 

now i tried Simple Avalon mm transfer but lots of Overhead.

Addrss

Read_Data,  Write_Data

Write, Read

 

 

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ShengN_Intel
Employee
456 Views

Hi,


May I know any further update or consideration?


Thanks,

Best Regards,

Sheng


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jjang
Beginner
446 Views

i just finish read Avalon mm Interface Spec Sheet . and i tried to make it. 

 Burst.png

 

 

 

1.  I Dened like that Nios.. 

1. QSYS.png

 

2. Nios Connection

 when Connection Initial Nios Core Settings don't have Burst Count [32] so i tried to make it

 - nios Caches and Memory Interfaces Data Cache Add Burstcount signal to data_master → Enable 

 

 - Avalon MM -Slave          <---->    NIOS Core Data Master 

 : Burst_Count [32]          <----->  : none

 : ReadDataValid [1]        <----->  : ReadDataValid [1]

: Addr [8]                            <---->  : Addr [14] 

: Read [1]                            <----> : Read [1]

: Read_Data[32]                <----> : Read_Data[32]

: wait_Request [1]            <----> : wait_Request [1]

: write [1]                           <----->: write [1]

: Write_Data [32]          <----->: Write_Data [32]  

:   none                               <-----> : Byte_Enable [4]

:  none                                 <----> : debug_mem_slave_debugaccess_to_roms [1]

2. hierachy.png

 

3. Nios_Settings.png

4. Data_Master_BurstCount.png

 

for burst transfer is it good connection?

 

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ShengN_Intel
Employee
432 Views

How about the byteenable signal (Master -> Slave)?


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ShengN_Intel
Employee
395 Views

Since there are no further feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.


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