How to use open IP cores without the megawizard

[Altera_Forum]

I must have missed something, because I can't seem to find anything on how to use an IP core from for example opencores. I keep finding things about use the megawizard to generate IP cores, but I just want to know a way how to use them without such a tool. 

Can you just download a core and then write some VHDL code around it and its ready to use? Then still I want to know how to do this, is it just placing the top entity of the core in your portmap and design? If its just that I can understand why I can't find anything about it, and otherwise I would like to know a place where to find such information. Since I can't believe there wouldnt be any information about this. I hope some one can help me and maybe others who also have this question.  Greets

[Altera_Forum]

A core is nothing more than bunch of vhdl/verilog files. Megawizard helps you to parameterize these files and some of them may be encrypted, but you should not care what is inside. Think about cores as black boxes, that do the work you need.

[Altera_Forum]

So its just as simple to look up what in and outputs the component has and integrate it in your system? I thought you would have to load stuff and do hard things to get it all in your system. So I was making it too difficult? 

Than I can understand why I couldn't find anything about it

[Altera_Forum]

If your system is in Quartus II, then just copy the source files to your project and connect properly inputs and outputs to your own part of design. For QSYS you need to use simple GUI to import the source files and create a tcl file for your core. This procedure is quick and easy.

[Altera_Forum]

Ah allright, sounds good, than I was making it harder than it is. Always good to know it's easier than you think. 

Thanks!