Running the IP generated test bench takes 420 usec of simulation time. I have a pretty good workstation and that 420 usec of simulation time takes about 3 hours. When I set up simulation options, I set calibration mode to Skip Calibration, but I noticed when observing the memory signals, it looks like it's running the calibration. It takes the EMIF controller 82 usec to start generating a memory clock. Then the memory reset toggles and the calibration process begins. After 350 usec, the cal_success flag goes high and the memory is ready for use. Once again, it seems like I can't turn off calibration, is this a bug in the software? Attached is a screenshot of the waveforms.
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(This message was posted on behalf of Intel Corporation)
Skip calibration mode will still run the calibration in ideal case. The details as below:
In Skip Calibration mode, the calibration processor assumes an ideal hardware environment, where PVT variations, board delays, and trace skews are all zero. Instead of running the actual calibration routine, the calibration processor calculates the expected arrival time of read data based on the memory latency values that you provide, thus reducing much simulation processing.
Thus, you will still see the clock running and calibration pass signal assert.
By the way, another interesting fact. My Platform design Arria 10 GX project has a PCIe HIP and some external memory connected to the EMIF controller. In Platform Designer, if I generate a system level testbench or just a EMIF example design, the simulation fails with multiple complications that relates to the EMIF interface when not using Abstract Phy. If I generate a EMIF Arria10 controller IP using the IP Catalog from the main Quartus window and generate a example design, the DDR4 simulation passes with or without using the Abstract Phy. So I examined the two generated memory models and found them to be different. As I drill down through the instantiations, the working memory model uses the altera_emif_ddrx_model.sv model. The non-functional memory model drills down to a different module called top_inst_emif_mem_bfm_ip_altera_conduit_bfm_181_tj245tq (for my design) and this file uses many function calls to generate the memory signaling. I'm not going to pursuit this any further since I found a workaround solution, just thought it might be interesting to your readers.
Thanks for the details. Your finding is correct.
When you turn off abstract PHY, the simulation expect a memory component that allow the interface to perform read/write.
The bus functional model that generate using Platform designer (Qsys) will not work like a memory model (eg read/write from specific address). Thus, you have to replace the generic memory model in the project altera_emif_ddrx_model.sv model to make it work.
However, for system level simulation (eg, PCIE + EMIF), it is recommend to run the simulation using abstract phy mode as this will save the simulation time.