I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

[WQIUS]

I download the design example “cv_GX_1ch_40b_3125mbps”，change the chip to mine（ 5CGXFC3B7F23C8N），the Channel 1 has error，how can I do？

[CheePin_C_Intel]

​Hi,

As I understand it, you encounter some issue with the CV XCVR. To ensure we are on the same page, would you mind to further elaborate on the following:

1. What is the Quartus version that you are using?
2. Are you using any devkit from Intel or your own board?
3. Mind share with me further the location where you downloaded the cv_GX_1ch_40b_3125mbps design example?
4. Mind further elaborate on the error that you are referring to? Some screenshots or slides explanation would be helpful for further understanding.

Thank you very much.

Best regards,

Chee Pin

[WQIUS]

Hi: As you see, I indeed encountered some problems, which come from the FPGA chip of 5CGXFC3B7F23C8N. When I use the GXB bank ,CH L1 always compile error. Here are the answers you established： 1. the Quartus version is 18.0; 2. my board; 3. cv_GX_1ch_40b_3125mbps design example , I download it in “interFPGA ”website “on-chip debugging design examples”; 4. the error is “14566 Could not place 1 periphery component（s） due to conflicts with existing constraints (1 channel PLL(s)” Hope you can help me . Looking forward to you reply. Best regards, Qiushi Wang —————————————————————— mobile ： 18810644922 email ：wangqiushi@cgnpc.com.cn

[Abe]

Can you try the following fix and see if it helps resolve this issue:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2017/error--14566---the-fitter-cannot-place-1-periphery-component-s--.html

[WQIUS]

Hi: I tried your advice, in the website you mentioned, the fix idea is “set_global_assignment –name AUTO_RESEVE_CLKUSR_CALIBRATION OFF” But ,when I open the .qsf file, there is not the information as above, and then I add it to the file, after recompile , the same error still comes out. —————————————————————— 王秋实 中广核研究院北京分院 技术支持部 联系电话：010-82193500-279 手机 ：18810644922 邮箱 ：wangqiushi@cgnpc.com.cn

[WQIUS]

王秋实 将撤回邮件“Abe answered you: I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error”。 1、本电子邮件及其附件所载之信息均为不公开信息，仅供指定的收件人收阅。如果您错误地接收了本电子邮件，请立即回复并通知发件人，并永久删除该电子邮件及其所有附件和销毁所有复印件。2、未经发件人许可，请勿对本邮件内容进行披露、复制、分发或使用。对于任何由此造成的后果，我公司将保留法律追究的权利。3、互联网通信不能保证及时性、安全性、无差错或无病毒。发送者不对本邮件及附件中的任何错误或遗漏承担责任。 1、The information in this email and any of its attachment is undisclosed. It is intended solely for the named addressee. If you have received this email in error, please reply to the sender and notify him/her of this immediately and permanently delete the email and all its attachments and destroy all copies of them. 2、Any disclosure, copying, distribution, or use of the contents of this email without the permission of the sender is prohibited. In the event of any consequence caused thereby, our company reserves the right to take legal action. 3、The Internet communication does not guarantee timeliness, security, error-free or virus-free. The sender shall not be held responsible for any mistake or omission in the e-mail and attachments thereof.

[WQIUS]

Hi: I tried your advice, in the website you mentioned, the fix idea is “set_global_assignment –name AUTO_RESEVE_CLKUSR_CALIBRATION OFF” But ,when I open the .qsf file, there is not the information as above, and then I add it to the file, after recompile , the same error still comes out. You can use the file to fix the error.

[WQIUS]

Hi: I reloaded the 14.0 version of the software

[WQIUS]

Hi: Is there a solution？ This GXB BANK, CH2(L1) in the 3 channels cannot compile ,can it be solved? —————————————————————— 王秋实 中广核研究院北京分院 技术支持部 联系电话：010-82193500-279 手机 ：18810644922 邮箱 ：wangqiushi@cgnpc.com.cn

[CheePin_C_Intel]

​Hi WQIUS,

Sorry for the delay. For your information, I have downloaded the cv_GX_1ch_40b_3125mbps.qar and tried to perform compilation in Q17.0 (since I do not have Q18.0 installed currently in my PC). After performing the auto-upgrade for IPs, removed all pin assignment as well as changing the parts to 5CGXFC3B7F23C8, I get into other Fitter errors which are different from yours. They are mainly related to unsupported PHY configuration and data rate. After fixing these errors, I am able to compile the design without Fitter error. Would you mind to share with me what are the changes that you have done to the cv_GX_1ch_40b_3125mbps.qar which would lead to your observation? This would be helpful for issue replication and further debugging.

Thank you.

Best regards,

Chee Pin

[WQIUS]

Hi: I re-downloaded quartus ii 17.0, and then opened the project in the attachment. This project was downloaded from the official website of the interFPGA, Without any modification, after upgrading to version 17.0, the chip type was changed to 5CGXFC3B7F23C8, and the VCCH_GXBL_USER_VOLTAGE/VCCH_GXBR_USER_VOLTAGE in the "gx_link_test_example.qsf" file was modified to 2.5V , set hssi_rx/hssi_rx(n) in pin planner is PIN_W2/PIN_W1, set hssi_tx/hssi_tx(n) is PIN_U2/PIN_U1, which is GXB BANK L1. Modify the custom PHY xcvr_custom_phy_0 parameter in gx_link_test_system QSYS, transceiver interface width :10, PCS-PMA interface width:10, Word aligner pattern length :10,word alignment pattern:1111100111. Based on the above changes, compile the project, the same error occurs. As belows: [X] Can you help me to see how my operation differs from your operation? Thank you Best wishes.

[WQIUS]

Bye the way, after I change the GXB BANK Channel to L2(namely PIN_R2/R1,PIN_N2/N1),recompile it,there is no error.

[WQIUS]

In my changes, I also change the data rate to 1000Mbps

[CheePin_C_Intel]

Hi WQIUS,

Thanks for your update on the details on changes. For your information, the reason of the previous unfit is because you have assigned the XCVR channels to the physical channel 1 of the GXB bank. In the selected part of yours, there is only 3 XCVR channels. Only physical channel 1 have the CMU PLL which can drive duplex XCVR. Therefore, you can only place your duplex XCVR channel to physical channel 0 or 2 so that you can have CMU PLL to provide high speed clock to your TX channels.

Please let me know if there is any concern. Thank you.

Chee Pin

[WQIUS]

Hi: thank you for your reply. According to your point of view, only channels 0 and 2 can use the CMU PLL, which provide a high-speed clock . But if I want to use channel 1 as a channel for fiber-optic communication(SFP), is it not feasible? thank you

[WQIUS]

If I want to use 0.1.2 three channels, can I use gxb without cmu pll? If I can use it, how to instantiate gxb？

[CheePin_C_Intel]

​Hi,

Yes, you are right. If you want to use the CMU PLL, you are left with only CH0 and 2 to use. If you want to use all the CH0, 1 and 2, you may explore into using external fPLL. You can use one fPLL to drive all the 3 CHs at the same data rate. If you are planning to use two fPLLs to support different data rate, you might need to create some simple test design to try out to see if it works as I am not sure if there is enough fPLL to drive the XCVR banks on the same side.

You may refer to the wiki design example on how to use external fPLL:

https://fpgawiki.intel.com/wiki/Cyclone_V_Transceiver_PHY_Basic_Design_Examples#Cyclone_V_Native_PHY_with_external_fPLL_design_example

[CheePin_C_Intel]

Hi,

Yes, your understanding is correctly. If you would like to CMU PLL, then you can only use CH0 and CH2. If you plan to use 3 of the duplex XCVR channels at the same data rate, then you can explore using external fPLL to drive all the 3 XCVR channels. Note that when you use the CH1 as duplex XCVR, then you would not have a CMU PLL because it is located in the RX channel.

You may refer to the following design example for further details:

https://fpgawiki.intel.com/wiki/Cyclone_V_Transceiver_PHY_Basic_Design_Examples#Cyclone_V_Native_PHY_with_external_fPLL_design_example

Note that in your selected part, there is only one 3-CH XCVR banks. If you would like to implement 2 different data rates, I am not sure if there are sufficient fPLL resources on the same side for your selected part, You might need to create test design to check on this.

Please let me know if there is any concern. Thank you.

Chee Pin

[WQIUS]

Hi: sorry to disturb you. There is a question for you to ask. Regarding the GXB channel test, it uses a differential crystal. How can I test if the differential crystal is working properly? In addition, If I use the transceiver toolkit to test GXB channel send and receive, do I need to add “JTAG to Avalon Master Bridge” in the program to find this channel in the transceiver toolkit?

[WQIUS]

Hi： Sorry to disturb you，there is still a question ask， I use the cyclone V（5CGXFC3B7F23C8N）chip， about the crystal size of the GXB required， how should I choose？can 125M be？LVDS or LVPECL？ Are there any special requirements？ —————————————————————— 王秋实 中广核研究院北京分院 技术支持部 联系电话：010-82193500-279 手机 ：18810644922 邮箱 ：wangqiushi@cgnpc.com.cn

[WQIUS]

Hi: Thank you for your guidance. I will learn according to your meaning. If I have any questions, I will ask for your help again. Thank you.