I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

[WQIUS]

I download the design example “cv_GX_1ch_40b_3125mbps”，change the chip to mine（ 5CGXFC3B7F23C8N），the Channel 1 has error，how can I do？

[WQIUS]

Hi： Now, I have a new question to ask you. In the file”AN585 page:3:PHY LOOPBACK ”, it mentioned the message to enable the loopback function in GXB: To set the sd_loopback bit , you need to do a configuration write to the PCS control register. Also, I learn that the custom PHY can set loopback function, if there is a detailed steps to follow to set the loopback function? And, I download the design examples “transceiver_toolkit_13_0sp1_qar”,in which there is a folder “cv_GX_1ch_40b_3125mbps”,I change it to 1000Mbps, and change the device, but when I run the transceiver toolkit, it always has some error, then, I delete the PLL in the top.v file ,and there is no error . As I do not set the loopback, I can only see the TX . So, what is this problem? And ,How can I set if I want to check the TX and the RX channel with loopback? (cyclone V： 5CGXFC3B7F23C8N) Thank you. —————————————————————— 王秋实 中广核研究院北京分院 技术支持部 联系电话：010-82193500-279 手机 ：18810644922 邮箱 ：wangqiushi@cgnpc.com.cn

[CheePin_C_Intel]

Hi,

Regarding your inquiries on setting the serial loopback in Custom PHY, for your information, you will need to perform register writing to enable the serial loopback. You may refer to the XCVR PHY IP user guide -> "PMA Control and Status Registers" -> "phy_serial_loopback" register for further details.

By the way, to ease your debugging, I would recommend you to create a new simple one channel test design with Custom PHY in RTL to avoid any dependency on the XCVR toolkit and design example.

You may try to refer to the following AV Custom PHY design to enable serial loopback:

https://fpgawiki.intel.com/wiki/Arria_V_Transceiver_PHY_Basic_Design_Examples#Arria_V_Custom_PHY_simple_ways_to_enable_internal_serial_loopback_design_examples

Please let me know if there is any concern. Thank you.

Chee Pin

[CheePin_C_Intel]

​Hi,

For the differential crystal, it is recommended for you to monitor with oscilloscope to check on the signal to see if meeting your expectation or specs.

As for the transceiver toolkit, to use transceiver toolkit with CV devices, you would need to use the example design from the following:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/on-chip-debugging.html

Ideally you should use the same version of Quartus with the design examples. However, you may try to compile the design in new Quartus and then try with transceiver toolkit.

Thank you.

[WQIUS]

Hi： May I ask you a question？ For The cyclone V device （as:5CGXFC3B7F23C8N）,How can I determine the GXB REFCLOCK ? LVDS or HCSL? Is there any requirement？

[CheePin_C_Intel]

​Hi,

The CV GXB refclk support IO standards ie 1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL, HCSL, and LVDS. You may select the IO standard based on your target requirement ie protocol compliant or the oscillator that you are using. You may refer to the device datasheet for further details on the CV refclk specs when cross check with the oscillators.

[CheePin_C_Intel]

​Hi,

If I understand you correctly, you are referring to the frequency and IO standard of the crystal for the GXB refclk. For your information, the CV GXB refclk support frequency from 27MHz - 550MHz and the IO standard supported are 1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL, HCSL, and LVDS. You may refer to the device datasheet for further details. Thank you.