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I2C SOPC (open)core for Quartus 10

Altera_Forum
Honored Contributor I
1,492 Views

Hello, 

 

Has anybody succesfully implemented an I2C SOPC core in Quartus 10.1 yet? 

 

The one from http://www.grigaitis.eu/?p=18 gives the following warning(s): 

Warning: oc_i2c_master_0.avalon_slave_0: Signal chipselect appears 2 times (only once is allowed) 

(And this one but that doesn't matter: Warning: oc_i2c_master_0: This classic module should be upgraded; right click in the Component List.) 

 

And the one from http://www.nioswiki.com/perihperals/opencores_i2c gives the following warning: 

Warning: opencores_i2c: set_interface_property: Interface export_0 does not have a parameter associatedClock 

 

I haven't actually tested any of them yet, but I like to know whether or not they still work with Quartus 10.1, before I start working with them. 

Or if there are any other options? 

 

My goal is to config a switch using I2C.
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2 Replies
Altera_Forum
Honored Contributor I
61 Views

Update and another question. 

The one from grigaitis compiles fine without any (weird) warnings. 

 

But that gives me another question, how do you constrain I2C? 

Can I just put them on false paths? 

 

Thanks.
Altera_Forum
Honored Contributor I
61 Views

To anwser my own questions (maybe it's helpful for someone else). 

You can set SCL and SDA (the two I2C "signals") as false paths. 

The core and software from http://www.grigaitis.eu/?p=18 works flawless with Quartus 10.1 and a Tundra Switch \o/.
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