IIR in DSP-Builder with modified multiplier LUT or multiplie accumulate

[Altera_Forum]

Hi, 

 I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someone give me a good type there or a Example for a IIR filter with LUT or with multiplie accumulate?    Thanks.

[Altera_Forum]

can you provide some extra information? do the filters have the same coefficients? what is the sample rate and available clock rate? how many bits are the data and coefficients? 

 you should be able to take HDL for an IIR and use LE based multipliers instead of DSP blocks by using synthesis attributes or instantiating MegaFunction multipliers.

[Altera_Forum]

the filterbank have 32 IIR-bandpassfilter with 32x16 coefficient. 

the application is a mp3-encoder/decoder in dsp-builder. I have resolt my schematic with LUT.  The audio-signal is sampled with 48kHz and the load of coeff in multiplier from LUT with 48kHz x 32 = 1.536MHz. I use Base clock (48kHz) and a derivate clock with 1/32 dimension --> 48kHz / (1/32) = 1.536MHz. But I d'ont can simulate, I have the following errormessage:  ********* Error reported by S-function 'sGeneric' in audio_path.mdl Two ports have different clocks clock_1.536MHz and clock_48kHz, where they should have the same  *********  my e-mail is maranello(at)hispeed.ch, so I can send you my mdl-file...

[Altera_Forum]

the two ports in the errormessage does mean the entry for the multiplier and adder...

[Altera_Forum]

I try to make two clocks with PLL, but without success...

[Altera_Forum]

I post now my mdl-file...

[Altera_Forum]

my mdl-file:

[Altera_Forum]

here the coeff for the LUT (load in matlab workspace).

[Altera_Forum]

I make a Simulation in matlab with the same clock of 48kHz, the simulation was correct. But with the signal compiler dsp-builder I became a error 

--> out of memory quartus-map.exe 1881 MByte   wath is the problem?

[Altera_Forum]

looks like the underlying Quartus application ran out of physical RAM in your machine.

[Altera_Forum]

my workstation is a x64 OS Win 7 Prof with 8 GB RAM, thats not normaly that a program go out of memory.  

Could you explain me how I can make settings in quartus or in dsp-builder for better work with the RAM?   Is the solution maybe Quartus 9.2 with DSP-Builder 9.2?   Thanks for your answer...

[Altera_Forum]

my workstation is a x64 OS Win 7 Prof with 8 GB RAM, thats not normaly that a program go out of memory.  

Could you explain me how I can make settings in quartus or in dsp-builder for better work with the RAM?  Is the solution maybe Quartus 9.2 with DSP-Builder 9.2?  Thanks for your answer... http://www.alteraforum.com/forum//proweb/misc/progress.gif

[Altera_Forum]

DSP Builder is only built for MATLAB 32-bit so it cannot take advantage of your full 8GB of RAM. i imagine the call to Quartus II also runs the 32-bit Quartus binary.

[Altera_Forum]

I found the failure, I has insert a bus conversation on the output from my IIR with "signed int 16-bit in/out and make settings in DPRAM also signed int 32x16 bit and not inferred. 

The reason was, I has to large information with always inferred settings, but is not important at the output from my IIR, when the signal is 205.12584 or only 205. Now the consuption of my RAM are about 1200MB...   Thanks...