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INTEL FPGA STRATIX 10GX

meerasahib
Beginner
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I have recently purchased the Intel fpga stratix10gx development kit.we are developing video accelerator for nvidia jetson agx  xavier platform.Here ,Interface between Intel FPGA and GPU Jetson xavier is PCIe .we are doing both upstream and downstream of video .Initially ,trying out to understand the PCIe link in PC  using example PCIe configuration file available in installer package.I am not able to detect the FPGA in PC as well us in Jetson which are running in ubantu 20.04.It seems that Our workstation not able to scan Intel FPGA .Please help us how to detect/enumerate/test PCie link .I want understand how Intel Stratix 10gX bring up happening with PCIe link.Kindly help to setup for bring up the Intel startix 10gx with PC as well as nvidia jetson agx xavier platform.

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wchiah
Employee
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Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel

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wchiah
Employee
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Hi,


First, please try warm reboot and check if the system is able to linkup or not.

Else I would suggest you to :


  1. Can I check with you if you do program the .sof file into your system ? Detail you may refer to Intel Stratix 10 user guide or video below https://www.youtube.com/watch?v=1Cgd5JjcCY0&ab_channel=IntelFPGA
  2. Could you please capture ltssmstate[5:0], currentspeed[1:0], lane_act[4:0] and link_up signal from Signaltap? This can help to confirm if the link training is up correctly.
  3. If the problem still not solve, I would like to suggest you to update your the Jetpack into latest version.


if still not workable,

  • We tested the design by using 1SM21BHU2F53E1VG in the past, and it can link up properly. I not sure what device OPN that you are using but you can try it as well.
  • This is a production device that same with the device in this link: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1... The 1SM21BHU2F53E2VGS1 is the engineering sample device, and the board is currently not available for testing.
  • When you generate the example design by using the PCIe IP AVMM GUI, did you select "Stratix 10 MX H-Tile ES1 FPGA Development Kit"?
  • Did you able to try it by using a different server/host? Besides, you may also try to use "Avalon ST Intel Stratix 10 hard IP for PCI express" or "Avalon-MM Intel Stratix 10 Hard IP for PCIe Express" from IP catalog to generate the example design and see if it can link up as Gen3X8 as expected and detect by the host.
  • This can help to rule out if there is a design example dependency.


Regards,

Wincent_Intel


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wchiah
Employee
443 Views

 

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?


Regards,

Wincent_Intel


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wchiah
Employee
406 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel

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