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IOPLL rst input

Altera_Forum
Honored Contributor II
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I instantiated an IOPLL in an Arria 10 SoC design and tried to tie the rst input to logic 0. Quartus Prime won't let me do that. I don't want to reset the PLL and the user guide does not say that a reset is required (although the pin has to be there). Why can't rst just be tied off to the inactive state? 

 

Thanks, 

Bob
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