IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

[Altera_Forum]

I found the following IP Core Resource Centers which have useful links to application notes, reference designs, online trainings, knowledge database and etc. You may find them useful:  

 Triple Speed Ethernet (TSE) http://www.altera.com/support/ip/interface-protocols/ips-inp-tse.html  Serial Digital Interface (SDI) http://www.altera.com/support/ip/interface-protocols/ips-inp-sdi.html  POS-PHY Level 4 (SPI4.2/PL4) http://www.altera.com/support/ip/interface-protocols/ips-inp-spi4.html  PCI Express (PCIE) http://www.altera.com/support/ip/interface-protocols/ips-inp-pcie.html  Serial RapidIO (SRIO) http://www.altera.com/support/ip/interface-protocols/ips-inp-srio.html  10-Gbps Ethernet (10GbE) http://www.altera.com/support/ip/interface-protocols/ips-inp-10gbe.html

[Altera_Forum]

Hi GuruDog, 

 Thank you for these documents.   Best regards,  Jeremy.  Press enter to look up in Wiktionary or ctrl+enter to look up in Wikipedia

[Altera_Forum]

Thank you for these useful links. 

 I do have a question though.  I downloaded and adapted the demo design for 10Gb Ethernet. This demo design includes a verilog Ethernet frame generator, a verilog Ethernet frame monitor, and instantiates an example 10Gb Ethernet IP. Various loopbacks are available. The demo design also includes a NIOS based SOPC system, but this is simply used for configuration (no OS, no TCP/IP stack).  With this design, I can (theoretically, at least!): - test a single board of mine (using internal loopback) - test 2 boards of mine (one sends and receives, the other one loops back)  Yet, I'd like to make a 3rd test. I would like to "ping" one of my board from a PC with minimum modification. My question is: do I really need to implement an OS, a Niche style TCP/IP stack? Is it naive to believe I can simply loopback the frames received from the PC into the transmitter with minimum byte analyze and overrides (no software)? Is there a design reference or a tutorial applicable here?  Thank you in advance!  Jankzov

[Altera_Forum]

Hi GuruDog, 

 Thanks for the links. I downloaded Triple Speed Ethernet (TSE) ref design but it is not compiling in Quartus v9.1 and more over I am not able to generate SOF(Program files in v8.0). It would be great if some one can help me. Pls Pls Pls   Warning: Can't generate programming files for project because design file "C:/altera/tse_datapath_reference_design/tse_ref_design/crcgen_altcrc.v" is encrypted. It does not have license file support that allows generation of programming files. Warning: Can't generate programming files for project because design file "C:/altera/tse_datapath_reference_design/tse_ref_design/crcchk_altcrc.v" is encrypted. It does not have license file support that allows generation of programming files.

[Altera_Forum]

Hi GuruDog, 

 The links are very helpful! Thank you very much.  How about SATA/SAS IPs? It seems that they should be at the same page.  I found one white paper and a couple of other Altera documents saying that SATA and SAS are supported. Then I tried Quartus II 9.1 and searched the IP directory and browsed the document directories, I could not find SATA and SAS like those you listed.  Any insights?  Thanks again,  Tom

[Altera_Forum]

hello all, 

 please create a new thread when you ask questions so everyone can see the title and try and help.  Tom, i don't think Altera has SATA or SAS cores, only their partners do.

[Altera_Forum]

This is a very good resource centre

[Altera_Forum]

thank you for links

[Altera_Forum]

3Q~~~~~~~~~

[Altera_Forum]

Hi GuruDog, 

 Thank you for these documents.   Best regards, jack hoa

[Altera_Forum]

thanks a lot

[Altera_Forum]

This is a very good resource centre ,thank you

[Altera_Forum]

thanks for your sharing 

  Will   chrome://livemargins/skin/monitor-background-horizontal.png chrome://livemargins/skin/monitor-background-vertical.png chrome://livemargins/skin/monitor-play-button.png

[Altera_Forum]

thank you for links

[Altera_Forum]

--- Quote Start ---  With this design, I can (theoretically, at least!): - test a single board of mine (using internal loopback) - test 2 boards of mine (one sends and receives, the other one loops back)  Yet, I'd like to make a 3rd test. I would like to "ping" one of my board from a PC with minimum modification. My question is: do I really need to implement an OS, a Niche style TCP/IP stack? Is it naive to believe I can simply loopback the frames received from the PC into the transmitter with minimum byte analyze and overrides (no software)? Is there a design reference or a tutorial applicable here?  --- Quote End ---    hi Jankzov,  You should have completed your project. I am trying the third test you did before. If you can share with me some experience. How did you connect the two boards with 10GbE design? In the document, for testing in hardware, they do not have generator/checker, so did you have to use the 'remote partner' that can generate, transmit, receive and check the data?   Thanks a lot.

[Altera_Forum]

update the new link for SDI IP and TSE IP:  

 TSE: https://www.altera.com/support/support-resources/intellectual-property/interface-protocols/triple-speed-ethernet/ips-inp-tse.html  SDI:  https://www.altera.com/support/support-resources/intellectual-property/interface-protocols/sdi/ips-inp-sdi.html

[Altera_Forum]

update for the new link for 10GE: 

 https://www.altera.com/support/support-resources/intellectual-property/interface-protocols/_10-gbps-ethernet/ips-inp-10gbe.html