I'm using ATX PLL, PHY IP and IOPLL IP for a proof of concept of a transceiver project.
The IP core was successful in generation without any errors/warnings.
My VHDL files are without any compile errors.
Now in compilation I only receive errors in all the *.ip files.
Error(13224): Verilog HDL or VHDL error at h_tile_phy.ip(1991): illegal identifier : '_hw'
Error(13224): Verilog HDL or VHDL error at h_tile_phy.ip(2262): literal 8000000000 exceeds maximum integer value
Error(13224): Verilog HDL or VHDL error at h_tile_phy.ip(3677): literal 288230376151711743 exceeds maximum integer value
Error(13806): VHDL syntax error at atx_pll.ip(1) near text <
Error(17578): VHDL error at atx_pll.ip(1011): literal 8000000000 exceeds maximum integer value
Error(13806): VHDL syntax error at pll.ip(1) near text <
Error(13927): VHDL syntax error at pll.ip(3982): _sortIndex is an illegal identifier in VHDL
So as I expect there should be errors in generation if there is something wrong and NOT in the compilation of IP components.
I'm using Quartus Prime Pro 19.1 for an Arria 10 GX DevBoard.
Thanks for your answer and your hint!
I created a new project where the issues did not come anymore.
After that I've compared both .qsf files to identify the root cause.
Root cause was the *.ip files where listed as 'VHDL/VERILOG file' and not as IP core file.
Thanks a lot!
This topic can be closed :)