IP Security with DS28E01 and Cyclone 4E - Altera Reference Design Integration Problem

[Altera_Forum]

Hello, 

 i try to integrate the Reference Design into my Design. I use the Dual-Purpose Pin "flash_nce/ncso as regular i/o after configuration" for the One Wire Interface. Externally i have an Pullup Resistance for One Wire Inteface (also the pin flash_nce/ncso). Firstly i use the "load_secret_key_ds28e01.mif" file for Secret Key Load to the Security Memory and program the .sof - file on FPGA via SignaltapII. I assume, that the Secret Key is now programmed in the Secure Memory. Secondly i use the "enabler_ds28e01.mif"-file with the hope, that i will see the "enable" Signal goes HIGH after FPGA-Configuration and the SHA1-Engine is done. After SHA1-Engine Reset i see in SignalTap2, that the statemachine in designfile "small_micro_32.vhd" does somewhat, but the OneWire IO always stay LOW and hence the "enable" Signal always LOW too.  Has someone succesfully used this Reference Design? Maybe i will try to use one normal IO for Onewire Interface...  The Reference Design is here http://www.altera.com/support/refdesigns/sys-sol/indust_mil/ref-des-secur-mem.html  Thanks in Advance!  Cheers   Tomy

[Altera_Forum]

I also used that ref design and I confirm it works perfectly. 

You only need to put matched keys in the loader and enabler projects before recompiling and generating the mif files. IIRC you also need to update a parameter in one of the hdl files with your actual system frequency. Do you have the correct pull-up resistor? It should be about 2k. Also check the onewire line is switching up/down for a while just after you configured the loader sof.

[Altera_Forum]

many thanks to you for your reply:) 

 As i see the loader and the enabler projects have the same source code, and .bdf file (!?), except the small_micro_32.vhd/program_mem/load_secret_key_ds28e01.mif for the loader project and /enabler_ds28e01.mif for the enabler. Right? One thing i find stranger, that the original reference design for the loader and the enabler project has differential secret key ?! I assume that is unintentional(!?).  So i copy all the required source code(small_micro_32.vhd; rng_8bits.vhd; program_mem.vhd; one_wire.vhd; adder.hvd) and .bdf file (sha1_engine.bdf); .qip - file (program_mem.qip; adder.qip) into my design.  I have tried a regular IO Pin (not the Dual Purpose Pin: flash_nce/ncso as regular i/o after configuration) for the One Wire Interface with PullUp = 1K. System Clock is 25MHz with a corresponding SYSCLOCK macro 25.000.000.  Firstly for Secret Key Load i changed only the program_mem/mem init/file name under MegaWizard Plug-In Manager with load_secret_key_ds28e01.mif and recompile and then i programm the .sof file onto the FPGA via SignalTap(Programmer).  After that, i hope and assume that the secret key resides now in the Secure Memory.  Secondly i do the same with only a change with enabler_ds28e01.mif, recompiling, re-programming the FPGA. But i see, the enable-Signal is always LOW.  In SignalTap for the loader project i see the One_Wire_data_io Pin always stays LOW when the Secure Memory is connected. But when the Secure Memory is not connected, then One_Wire_data_io Pin can toggle. Somehow the Secure Memory always drives the IO-Pin LOW(!?).  Please see the SignalTap ScreenShot attachment.  Thanks in Advance  Cheers  Tomy

[Altera_Forum]

I checked the Altera reference design against my own project and I confirm I changed nothing except the secret key and the clock frequency; 

so I think also yours should work as is. Make sure the secure memory is properly connected and working. Onewire signal must be normally high. As I said before, first of all you should check the onewire signal is switching when you configure the Loader project. On my board I see bursts of 80us pulses for a few tens of ms just after I configure the sof file.

[Altera_Forum]

Hi Cris, 

 thank you for taking time:)  I have wrongly identified the two Pins OneWire IO and the Ground. Therefore this didnt work. Now it works with one normal FPGA-IO, but not with the Dual-Purpose Pin flash_ncs. I use Quartus 13.0.1 sp1.  For Config Flash i use EPCQ in AS scheme, but in Quartus Setting GUI i must do PS Setting then compile is done without fitter error.  Thank you in Advance!  Chees

[Altera_Forum]

Hello, 

 i'm back!:) I have succsesfully tested with Dual-Purpose Pin Flash_nCS too.  Now i'm looking for a Software Tool (for Labview maybe) for volume programming secret Key into the Secure Chip. Is there a tool like that?  Thanks in advance!  cheers  Tomy

[Altera_Forum]

--- Quote Start ---  I also used that ref design and I confirm it works perfectly. You only need to put matched keys in the loader and enabler projects before recompiling and generating the mif files.   --- Quote End ---   Please explain how to generate the .mif files. There is not a word about it in the "Cyclone III FPGA Design Security Solution Using SHA-1 with DS28E01 Reference Design User Guide". I don't see any .mif emerging after compiling loader and enabler projects ... How did You treat two .mif files ( dated 2007 ), that were included in the original project?   --- Quote Start ---   Also check the onewire line is switching up/down for a while just after you configured the loader sof.  --- Quote End ---   How do You configure the loader .sof ?  Use the Quartus Programmer with "Initiate configuration after programming" option enabled?

[Altera_Forum]

--- Quote Start ---  Hi Cris,  I have wrongly identified the two Pins OneWire IO and the Ground.   --- Quote End ---    Was it because the picture in datasheet is rather confusing? Is it really Bottom view instead of Side view, that is shown? Was DS28E01 damaged after swapping IO and GND? https://www.alteraforum.com/forum/attachment.php?attachmentid=8958

[Altera_Forum]

--- Quote Start ---  Please explain how to generate the .mif files. There is not a word about it in the "Cyclone III FPGA Design Security Solution Using SHA-1 with DS28E01 Reference Design User Guide". I don't see any .mif emerging after compiling loader and enabler projects ... How did You treat two .mif files ( dated 2007 ), that were included in the original project?   --- Quote End ---   You don't need to generate nor modify the .mif files. They are included in the project, ready for use. This is the ROM program code for the processor and they are referenced in program_mem.vhd.    --- Quote Start ---   How do You configure the loader .sof ?  Use the Quartus Programmer with "Initiate configuration after programming" option enabled?  --- Quote End ---   What's the problem here? You configure with Quartus Programmer like any other design. You configure with the "security_load" program in order to store the key into the device: this is needed only once; then you should only use the "security_enabler" configuration, which checks the correctness of the security key against that previously stored into the device.

[Altera_Forum]

--- Quote Start ---  Hi Cris,  thank you for taking time:)  I have wrongly identified the two Pins OneWire IO and the Ground. Therefore this didnt work. Now it works with one normal FPGA-IO, but not with the Dual-Purpose Pin flash_ncs. I use Quartus 13.0.1 sp1.  For Config Flash i use EPCQ in AS scheme, but in Quartus Setting GUI i must do PS Setting then compile is done without fitter error.  Thank you in Advance!  Chees  --- Quote End ---    Hi~I have the same problem as you ,I are using EP4CE6E22 + EPCS4 now, and the quartus2 version is 13.1,sadly it doesn't work, i check the pins connect ,pins voltage(3.3lvttl),and the tow design files i don't edit expect sys_clock or security_key, Is there any different about the load file and enable file ? what kind of pull-up resistor do you connect? 2k?22k?  I'm looking for your help. thank you in advance!