FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

IP UART Core

Altera_Forum
Honored Contributor II
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Hi everyone!  

 

I am a Student and I am implement the IP Uart Core on SOPC, but i don't know how to IP core connect to Avalon.  

So Anybody Can support me (document, verilog code,.v..v) 

 

Thanks you
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Altera_Forum
Honored Contributor II
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i also hava the problem that like you. So, can anyone help me?... Thanks so much..!!

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Altera_Forum
Honored Contributor II
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You can find the Avalon Specification here: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

You can also read section II.7 of the Quartus manual about creating your QSys components: http://www.altera.com/literature/hb/qts/qsys_components.pdf 

There is also a checksum generator component example that uses several Avalon interfaces here: http://www.altera.com/support/examples/nios2/exm-checksum-acc.html
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