IP behind AvaloneMM Pipeline Bridge- Latency

[Altera_Forum]

HI all, 

 This is my first time using avalonMM pipeline bridge.  I face some problem that my IP which connect behind the AvalonMM pipeline bridge always receive incorrect data when Nios communicate with it.  I found out the AvalonMM pipeline bridge data and addr were changing while the write and chipselect is still remain high. ( Or the wr and chipselect were high for 2 cycle)  http://img.photobucket.com/albums/v284/jimleo2002/AvMM_Pipeline_1.jpg   During the setup of the AvalonMM pipeline bridge in SOPC, all the 3 pipeline options were been selected. I assume that it shall pipeline all the signals atleast the basic one, wr,read,wrdata,readdata, and wait request, chipselect.   But from signal tap, the thing doesn't happen as expected. Can anyone point me out where has gone wrong? thanks you.   JIM

[Altera_Forum]

To top-up that the system clock for the above transfer is sys_pll-c0. 

 Thanks  JIM

[Altera_Forum]

Hi, 

 I am not sure if this is going to be helpful. According to my old experience, the avalon bridge only operates in byte addressing mode(data bus itself can be variable). Thus you need to discard some LSBs of address as follows:  avalon datawidth bridge datawidth discard address bits 32 ........................32................... 2 LSB bits 32 ....................... 16................... 1 LSB bit 32 ........................8....................... none   Nios aligns addresses from byte to byte. Thus I expect the address to move from 0 to 1 to read two bytes across the bridge if your avalon datawidth is 16.

[Altera_Forum]

Hi Kaz,  

 THanks for your reply.  You are right that the root cause is due to the data bus is 16bits and the byte adressing mode.  I didn't notice there is a warning in SOPC that IP data bus of 16bits will cause spurios write. After I change the data bus to 32bits width, the read & write operation run as normal.  Thanks again to Kaz