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Hello All,
I use the Cyclone IV FPGA to realize bandpass FIR. And I use the quartus 11.0 version. The configuration of IP core FIR are as follows: Filter Type: bandpass windows type: hanning coefficents: 64 Sample rate: 1MHz Cutoff Frequ.1: 5Hz Cutoff Frequ.2: 200Hz Input and output bit width: 8 clk: 1MHz reset_n: 1 ast_sink_data[7..0]: ad_data, which are from AD, the AD frequecy is 15KHz coef_set: 1 ast_sink_valid: 1 ast_source_ready: 1 ast_sink_error: 0 ast_souuce_data[7..0]: 0, which always keep 0 whatever i change the input. Would you please help check what are the problems? Very urgency:confused:. Thank you very much. http://www.alteraforum.com/forum/attachment.php?attachmentid=11576&stc=1Link Copied
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