FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5984 Discussions

IP core FIR Configuration Problems

Altera_Forum
Honored Contributor II
785 Views

Hello All, 

 

I use the Cyclone IV FPGA to realize bandpass FIR. And I use the quartus 11.0 version. 

 

The configuration of IP core FIR are as follows: 

Filter Type: bandpass 

windows type: hanning 

coefficents: 64 

Sample rate: 1MHz 

Cutoff Frequ.1: 5Hz 

Cutoff Frequ.2: 200Hz 

Input and output bit width: 8 

 

 

clk: 1MHz 

reset_n: 1 

ast_sink_data[7..0]: ad_data, which are from AD, the AD frequecy is 15KHz 

coef_set: 1 

ast_sink_valid: 1 

ast_source_ready: 1 

ast_sink_error: 0 

 

ast_souuce_data[7..0]: 0, which always keep 0 whatever i change the input. 

 

Would you please help check what are the problems? Very urgency:confused:. Thank you very much. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=11576&stc=1
0 Kudos
0 Replies
Reply