Hi,Can anyone out there point me in the right direction so I can add hardware timeout capability to a custom IP core? We plan to generate an IP for a Stratix-IV and would like to have the customer evaluate it prior to purchase. Thanks, Jeff
Thanks for the quick response! Please note that our flow is different than the average AMPP partner. Although we do offer fixed functions,our core business is a design service where we convert c code to VHDL. We typically perform a test run to showcase our capabilities and report out on the results. The next step we have in mind is to allow customers to evaluate the test run algorithm on their own hardware platforms. So is there a way we can add user logic to our IP to program an internal watchdog timer that will shut down (or disable) the FPGA after specified amount of time? Perhaps you can recommend a better approach if this is not feasible. We are hoping to avoid a licensing scheme. Please excuse my lack of knowledge as my background is with Xilinx. Thanks, Jeff
What you have described sounds almost exactly like OpenCore method (with time-limited .SOF programming files unless "licensed") and the only way to obtain access to that is through AMPP I believe. My suggestion would be to contact Altera directly and see what they say about your situation.I guess ideally you would issue your customer an OpenCore unlicensed version they can evaluate with in the lab, and then later issue a non-OpenCore version after they have paid their invoices in order to avoid issuing FlexLM license. Other than that, I think you're looking at rolling your own. I'm not sure you could disable the entire FPGA from your block, but you could certainly make your own block become unresponsive after the timeout.