IRIG/PPS Integration

[Altera_Forum]

I'm looking to integrate an IRIG-B(IEEE 1344 version) and PPS (Pulse Per Second) into a Stratix IV GX development board. Does anyone know of existing IP or freely available code to handle IRIG-B timecode reading? Also, any pointers on to how use PPS to discipline a clock on an FPGA for would be much appreciated.  

 Thanks

[Altera_Forum]

--- Quote Start ---  I'm looking to integrate an IRIG-B(IEEE 1344 version) and PPS (Pulse Per Second) into a Stratix IV GX development board. Does anyone know of existing IP or freely available code to handle IRIG-B timecode reading? Also, any pointers on to how use PPS to discipline a clock on an FPGA for would be much appreciated.    --- Quote End ---  The time codes are just serial port strings right? Linux knows how to deal with them, so boot Linux on a NIOS II core and read them there.  You would not use the 1pps to discipline the FPGA clock, you would use the disciplined 10MHz from a GPS unit as the reference clock to the FPGA; you just need to buy a GPS unit with both 1pps and 10MHz output. Meinberg makes nice ones  http://www.meinberg.de/english/  Cheers, Dave

[Altera_Forum]

Dave,  

 Thanks much for your response!   I should clarify, I already have a GPS device, very similar to the one you suggested, that has an IRIG B, PPS and 10 MHz outputs. The objective is to incorporate a highly precise (<30ns) UTC time into the FPGA for use in network centric application which is implemented in verilog.   I'll say this cautiously, how I *think* this could be done is to create a separate clock/counter on the FPGA that contains a highly accurate UTC time. I envision this clock as having two 32 bit parts. The first or whole part would be an even number of seconds past epoch. The second would be a fractional representation of the current second. In order to do that I know I have to read the IRIG output which gives me the whole portion, and then the PPS when used in conjunction with the FPGA clock should give me the fractional part. I was hoping to get a pointer to an existing IRIG timecode reader, and then get some advice overall on what algorithms would solve this.

[Altera_Forum]

--- Quote Start ---   I should clarify, I already have a GPS device, very similar to the one you suggested, that has an IRIG B, PPS and 10 MHz outputs. The objective is to incorporate a highly precise (<30ns) UTC time into the FPGA for use in network centric application which is implemented in verilog.    --- Quote End ---  The 1pps is synchronous to the 10MHz signal, so you already have a precise knowledge of when time increments. You just need to read the IRIG code within the right second.  In our systems, we have a 1pps from GPS down a backplane. Linux sees this 1pps, so accurately knows when time progresses. NTP is then used to fill in the time 'most significant values' of time, i.e., the year, day, hours, minutes, and second.    --- Quote Start ---   I'll say this cautiously, how I *think* this could be done is to create a separate clock/counter on the FPGA that contains a highly accurate UTC time. I envision this clock as having two 32 bit parts. The first or whole part would be an even number of seconds past epoch. The second would be a fractional representation of the current second. In order to do that I know I have to read the IRIG output which gives me the whole portion, and then the PPS when used in conjunction with the FPGA clock should give me the fractional part. I was hoping to get a pointer to an existing IRIG timecode reader, and then get some advice overall on what algorithms would solve this.  --- Quote End ---  Store time using a struct timespec (read the man page).  Count 10MHz periods every second, and when someone/thing asks the hardware for 'the time', convert the counter reading into a timespec and return that value. Your counter really only needs to count modulo 1s, but you can add a seconds count too.   For example, in one of my systems I have a pair of 32-bit registers with a full timestamp (timespec). Real-time data and the timestamp are DMAed under hardware control to DDR memory in the address map of a Linux processor. The Linux processor consume data packets in non-real-time (but at a sustained rate), and can use the timestamps to know precisely when the data was captured.   Cheers, Dave