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Altera_Forum
Honored Contributor I
731 Views

Implementing Cache Memory for Custom Logic

How can I implement a cache memory for look-up purposes which works with my custom logic, not Nios or ARM? 

I have implemented different cache architectures using VHDL or Verilog, pipelined them, worked on the performance, but they cannot afford my performance requirements. On the other hand Nios has a cache option. This means that there should be a way which implements an efficient cache memory. If there was a cache IP like SDRAM or DRAM, etc it would be nice; nonetheless it seems there is no such option. 

 

How could I instance a cache memory using Altera/FPGA features which communicates with my custom logic? 

Please keep in mind that there is no Nios or ARM processor. 

 

Thanks
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Altera_Forum
Honored Contributor I
31 Views

I'm not aware of any bundled IP that would implement a cache as you would like. 

 

What you would need to do is either create your own, or pull together enough pieces from the internet to create your own. Skimming opencores.org, nothing jumps out as immediately usable. There is an empty project for something which would have most likely been an exact fit for you: http://opencores.org/project,level2_cache_nios_iie 

 

Good luck!
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