Inconsistant number of messages under Design Assistant Rule D101 inside DDR IP

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Running Quartus I 13.0.0 64-bit on a CycloneIV CE design in two revisions (an EP4CE40F23C6 device and a EP4CE75F23C7 device). I am getting Rule D101 violations from within the altera_ddrif IP but ONLY in the EP4CE75F23C7 revision. All constraints generated by the Megawizard have been applied to both revisions. What's interesting is that either the Design Assistant tool or Quartus is reporting an inconsistent number of violations. Example, from the EP4CE40F23C6 run: 

 Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). found 12 asynchronous clock domain interface structure(s) related to this rule.  Critical Warning (308012): Node "biu:biu|gcr_reg[0]"  Critical Warning (308012): Node "ddrc:ddrc|ddr_int_reset_reg[28]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[4]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[12]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[20]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[28]"   Now from the EP4CE75F23C7 run: Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). found 12 asynchronous clock domain interface structure(s) related to this rule.  Critical Warning (308012): Node "biu:biu|gcr_reg[0]"  Critical Warning (308012): Node "ddrc:ddrc|altera_ddrif:altera_ddrif|conv_ddr2:conv_ddr2_inst|conv_ddr2_controller_phy:conv_ddr2_controller_phy_inst|conv_ddr2_phy:conv_ddr2_phy_inst|conv_ddr2_phy_alt_mem_phy:conv_ddr2_phy_alt_mem_phy_inst|conv_ddr2_phy_alt_mem_phy_mimic:mmc|mimic_done_out"  Critical Warning (308012): Node "ddrc:ddrc|altera_ddrif:altera_ddrif|conv_ddr2:conv_ddr2_inst|conv_ddr2_controller_phy:conv_ddr2_controller_phy_inst|conv_ddr2_phy:conv_ddr2_phy_inst|conv_ddr2_phy_alt_mem_phy:conv_ddr2_phy_alt_mem_phy_inst|conv_ddr2_phy_alt_mem_phy_mimic:mmc|mimic_value_captured"  Critical Warning (308012): Node "ddrc:ddrc|ddr_int_reset_reg[28]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[4]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[12]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[20]"  Critical Warning (308012): Node "i2s:i2s|icr_reg[28]"  Critical Warning (308012): Node "ddrc:ddrc|altera_ddrif:altera_ddrif|conv_ddr2:conv_ddr2_inst|conv_ddr2_controller_phy:conv_ddr2_controller_phy_inst|conv_ddr2_phy:conv_ddr2_phy_inst|conv_ddr2_phy_alt_mem_phy:conv_ddr2_phy_alt_mem_phy_inst|conv_ddr2_phy_alt_mem_phy_write_dp_fr:full_rate_wdp_gen.wdp|dq_oe_2x[0]"  Critical Warning (308012): Node "ddrc:ddrc|altera_ddrif:altera_ddrif|conv_ddr2:conv_ddr2_inst|conv_ddr2_controller_phy:conv_ddr2_controller_phy_inst|conv_ddr2_phy:conv_ddr2_phy_inst|conv_ddr2_phy_alt_mem_phy:conv_ddr2_phy_alt_mem_phy_inst|conv_ddr2_phy_alt_mem_phy_write_dp_fr:full_rate_wdp_gen.wdp|dq_oe_2x[1]"  Critical Warning (308012): Node "ddrc:ddrc|altera_ddrif:altera_ddrif|conv_ddr2:conv_ddr2_inst|conv_ddr2_controller_phy:conv_ddr2_controller_phy_inst|conv_ddr2_phy:conv_ddr2_phy_inst|conv_ddr2_phy_alt_mem_phy:conv_ddr2_phy_alt_mem_phy_inst|conv_ddr2_phy_alt_mem_phy_write_dp_fr:full_rate_wdp_gen.wdp|dq_oe_2x[2]"  Critical Warning (308012): Node "ddrc:ddrc|altera_ddrif:altera_ddrif|conv_ddr2:conv_ddr2_inst|conv_ddr2_controller_phy:conv_ddr2_controller_phy_inst|conv_ddr2_phy:conv_ddr2_phy_inst|conv_ddr2_phy_alt_mem_phy:conv_ddr2_phy_alt_mem_phy_inst|conv_ddr2_phy_alt_mem_phy_write_dp_fr:full_rate_wdp_gen.wdp|dq_oe_2x[3]"    The -40 run SAYS there are 12 violation but is listing only 6. The -75 run SAYS there are 12 D101 violation and is indeed reporting 12.  My Questions are:  1) Why am I getting ANY D101 violations from generated Altera-base IP?? 2) What's up with the reporting??