Inferred Latches in CVI II core with Quartus Pro v18.1

[Andy1]

Hi,

There are currently 2 warning in the synthesis report for the CVI II VIP core:

Warning(16864): Verilog HDL warning at alt_vip_cvi_av_st_output.sv(283): arg0 may be used uninitialized in static subprogram send_frame_packet and create unintended latch behavior 

Warning(13228): Verilog HDL or VHDL warning at alt_vip_cvi_av_st_output.sv(602): latch inferred for net send_frame_packet.arg0.empty 

Are these warnings known issues or can they be ignored due to optimisation?

Kind Regards,

Andy

[CheePin_C_Intel]

Hi Andy,

Based on my understanding, these warnings can be ignored due to optimization. Just would like to check with you if you observe any issue running your design in simulation and hardware with CVI II?

Please let me know if there is any concern. Thank you.