I am using VHDL code to infer a RAM IP of stratix 10. There are two choices to initialize RAM: use a function as provided by the VHDL template, or use attribute as shown in following:
type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";
My problem is that the initialization file is optional. Before we set the ip parameter of "init_file" to "unused" when we don't want a initialization file. Now we are moving to VHDL to infer a RAM block. But "unused" doesn't work for the attribute above. It has to be an effective file name with the attribute. Is there any solution for this one?
We use the RAM as a generic_ram in our project. And the initialization file is optional depends how the upper layer uses it. And we also have other project use the generic_ram as well which is on Arria 10. They are still using the old generic_ram which is not inferring RAM with VHDL, but setting ip parameters of RAM IP. They have the option to use or not use initialization file. For the compatibility, we also need this option.We are trying to use inferring RAM because this method is device independent and parameters independent, and it is easier to maintain when we move from device to another, such as the situation we have now is moving from Arria 10 to Stratix 10, there are a lot of extra work to update the device related primitives. Please let me know if you have any idea.
The only thing I can think of would be if you could make the attribute conditional. Google brought up this though it's not clear if it works or not and I don't know if it would synthesize in Quartus:
That might give you a starting point.
Thanks a lot for you recommendation. The problem for the method provided by the link is that the attribute only works inside the scope of generate. That means I need to repeat my generic_ram twice for with init_file and without init_file, and also I have to declare my data type and ram signal inside the generation, twice. My code is pretty long now, because I have all ram function in one file, such as single/dual port, single/dual clock, with/without byte enable, mixed ports or non mixed ports. Upper level uses different generic settings to choose the function of ram. So, it seems not a good solution for me. Thank you anyway. Please let me know if you have other ideas.
Thanks Steven for the guidance.
As I understand it, Quartus will expect you to specify the mif file whenever you specify the ram_init_file attribute. The current available workarounds would be as discussed above by Steven:
- Use RAM IP
- Use VHDL infer RAM but no specify the init_file attribute
- Use the conditional attribute
Sorry for the inconvenience.