Intel Agilex 7 FPGA R-Tile Multi-Channel DMA IP for PCIe Design Example fail in hardware testing

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Intel Agilex 7 FPGA R-Tile Multi-Channel DMA IP for PCIe Design Example fail in hardware testing

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This is an issue sharing, related to Agilex 7 FPGA R-tile MCDMA PCIe IP design example:

After programming the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example targeting the Intel® Agilex 7 FPGA R-Tile devices A0 or B0 die revision, the PIO tests will fail, and the DMA tests report queue reset failures.
DK-DEV-AGI027RES : AGIB027R29A1E2VR0 = A0 die revision.
DK-DEV-AGI027R1BES : AGIB027R29A1E2VR3 = B0 die revision.

Solution:

A patch is available to fix this problem in the Intel® Quartus® Prime Pro Edition Software version 22.4

Regenerate and recompile the test design after installing the patch.

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