Intel DisplayPort Arria 10 Sample Project Not Simulating Correctly in Aldec Active-HDL

[DZuck1]

Hi,

I am trying to simulate the Intel DisplayPort Arria 10 Sample Project(Quartus Prime v17.0) in Aldec Active-HDL (v10.3 64 bit) and don't think the simulation is working correctly.

The testbench executes all the way to the end with CRCs reported back to be all 0's for R, G & B. The vbid[3] - NoVideoStream_Flag is high during the entire simulation.

All of the signals mentioned in Figure 36 of UG-01131 (RX Video Waveform) are static for the entire simulation. I would expect the received video to look similar to the timing diagram of that figure.

Is there something wrong with the simulation or am I not setting it up correctly?

[watari]

Hi DZukc1

Signal "rx_vid_clk" is input signal and this frequency is ex. 162MHz.

So, would you input rx_vid_clk as 162MHz ?

This module (dp_sink) is generated some signals (ex. rx_vid_sol, rx_vid_eol, rx_vid_sof, r_vid_eof and so on) by rx_vid_clk.

BTW, if rx_vid_clk already toggled, would you wait for one frame ?

These signals are generated by MSA, VBID and so on.

Best regards

[DZuck1]

I expect to some transitions on rx_vid_sol, rx_vid_eol, rx_vid_sof, r_vid_eof, rx_vid_valid and rx_vid_data.

[watari]

I see.

Would you make sure rx_parallel_data signal on native_phy_rx, if it exist ?

I'm using DP Sink IP on Arria V.

So, it might not exist this module. But different name...

Best regards,

[DZuck1]

rx_parallel_data exists and is toggling.

[watari]

I see.

Would you make sure CDC setting at parameter in this IP ?

This module has many CDC logic.

If clock frequency setting is wrong, DP Sink malfunction.

Best regards,

[DZuck1]

I used the User Guide's process to generate the example design and that is what I am trying to simulate.

[BoonT_Intel]

Hi Sir, do you have chance to try the simulation with latest version 18.1 or other simulator like modelsim?

By the way, Arria 10 DP do not have CDC or CRC setting.

[DZuck1]

The only simulator I have access to is Aldec Active-HDL. The displayport core has a debug CRC setting that can be enabled to confirm the data received into the core. The sample design enables it by default. The User Guide shows that the CRC shouldn’t be 0.

[DZuck1]

I have tried to run this simulation using the pro version 18.1 and it still did not work correctly in Aldec.

[DZuck1]

Here is what Aldec prints out during the simulation: # KERNEL: start_main_link # KERNEL: start_test_main_link # KERNEL: Testing active line = 256 # KERNEL: Testing lane count = 4 # KERNEL: Testing Link HBR2 Rate (RX reconfig) # KERNEL: Testing Link HBR2 Rate (TX reconfig) # KERNEL: Testing maximum Vod and minimum pre-emphasis (TX analog reconfig) # KERNEL: Testing Link HBR2 Rate Training Pattern 1 # KERNEL: Testing Video Input Frame Number = 00 # KERNEL: Testing Link HBR2 Rate Training Pattern 2 # KERNEL: End Testing Link HBR2 Rate # KERNEL: Testing Link HBR Rate (RX reconfig) # KERNEL: TX Frequency Change Detected, Measured Frequency = 135 MHz # KERNEL: RX Frequency Change Detected, Measured Frequency = 135 MHz # KERNEL: Testing Link HBR Rate (TX reconfig) # KERNEL: Testing maximum Vod and minimum pre-emphasis (TX analog reconfig) # KERNEL: Testing Link HBR Rate Training Pattern 1 # KERNEL: Testing Video Input Frame Number = 01 # KERNEL: Testing Video Input Frame Number = 02 # KERNEL: Testing Link HBR Rate Training Pattern 2 # KERNEL: End Testing Link HBR Rate # KERNEL: Testing Link RBR Rate (RX reconfig) # KERNEL: TX Frequency Change Detected, Measured Frequency = 67 MHz # KERNEL: RX Frequency Change Detected, Measured Frequency = 67 MHz # KERNEL: Testing Video Input Frame Number = 03 # KERNEL: Testing Link RBR Rate (TX reconfig) # KERNEL: Testing minimum Vod and pre-emphasis (TX analog reconfig) # KERNEL: Testing Link RBR Rate Training Pattern 1 # KERNEL: Testing Video Input Frame Number = 04 # KERNEL: Testing Link RBR Rate Training Pattern 2 # KERNEL: End Testing Link RBR Rate # KERNEL: Testing Link HBR2 Rate (RX reconfig) # KERNEL: TX Frequency Change Detected, Measured Frequency = 40 MHz # KERNEL: RX Frequency Change Detected, Measured Frequency = 40 MHz # KERNEL: Testing Video Input Frame Number = 05 # KERNEL: Testing Link HBR2 Rate (TX reconfig) # KERNEL: Testing minimum Vod and pre-emphasis (TX analog reconfig) # KERNEL: Testing Link HBR2 Rate Training Pattern 1 # KERNEL: Testing Video Input Frame Number = 06 # KERNEL: Testing Link HBR2 Rate Training Pattern 3 # KERNEL: TX Frequency Change Detected, Measured Frequency = 135 MHz # KERNEL: RX Frequency Change Detected, Measured Frequency = 135 MHz # KERNEL: End Testing Link HBR2 Rate # KERNEL: Testing bpc = 1 # KERNEL: Testing Video Input Frame Number = 07 # KERNEL: SINK CRC_R = 0000, CRC_G = 0000, CRC_B = 0000, # KERNEL: SOURCE CRC_R = 0000, CRC_G = 0000, CRC_B = 0000, # KERNEL: Pass: Test Completed # RUNTIME: Info: RUNTIME_0070 a10_dp_harness.sv (1079): $stop called. Here is what is in the user guide: [https://www.intel.com/content/dam/altera-www/global/en_US/documentation/ufa1511788563556/ysy1475805841999.png]

[BoonT_Intel]

Thanks!

I run the simulation in modelsim_se edition and I also see the same observation (all zero). Let me check further on this.

But frankly speaking, for DP, usually we directly validate the IP on actual hardware and seldom run the simulation.

[DZuck1]

I am trying to re-run it with Quartus 18.1 and Aldec 10.5a but am not hopeful that it will work. I am a little curious why the text output of the testbench in the user guide is different than mine. The user guide has a measured frequency of 270 MHz which my simulation does not have. My simulation has 135 MHz twice and the user guide has it only once.

[BoonT_Intel]

I found that turn on Support CTS test automation in both Sink and Source will give a value to CRC. Tried this with modelsim and it is working now. # Testing bpc = 1 # Testing Video Input Frame Number = 04 # Testing Video Input Frame Number = 05 # Testing Video Input Frame Number = 06 # Testing Video Input Frame Number = 07 # Testing Video Input Frame Number = 08 # Testing Video Input Frame Number = 09 # Testing Video Input Frame Number = 0a # SINK CRC_R = 1015, CRC_G = 1015, CRC_B = 1015, # SOURCE CRC_R = 1015, CRC_G = 1015, CRC_B = 1015, # Testing Video Input Frame Number = 0b # Pass: Test Completed

[DZuck1]

I found the same: # KERNEL: Testing Link HBR2 Rate Training Pattern 3 # KERNEL: TX Frequency Change Detected, Measured Frequency = 135 MHz # KERNEL: RX Frequency Change Detected, Measured Frequency = 135 MHz # KERNEL: End Testing Link HBR2 Rate # KERNEL: Testing bpc = 1 # KERNEL: Testing Video Input Frame Number = 07 # KERNEL: Testing Video Input Frame Number = 08 # KERNEL: Testing Video Input Frame Number = 09 # KERNEL: Testing Video Input Frame Number = 0a # KERNEL: Testing Video Input Frame Number = 0b # KERNEL: Testing Video Input Frame Number = 0c # KERNEL: SINK CRC_R = 9b40, CRC_G = 9b40, CRC_B = 9b40, # KERNEL: SOURCE CRC_R = 9b40, CRC_G = 9b40, CRC_B = 9b40, # KERNEL: Testing Video Input Frame Number = 0d # KERNEL: Pass: Test Completed Thank you for the help!