I am trying to generate the simulation HDL for the Intel DisplayPort example project for the Stratix 10. I am consistently getting the same error message (attached). I have tried changing the number of lanes, speed, Verilog/VHDL and with/without PCR and it always fails at the same spot.
I even tried upgrading from Quartus Pro v19.1 to v19.2 and it still failed. Am I doing something wrong? I cannot generate the simulation data for some of the bitec encrypted cores manually and this is the only way to do it.
I am able to generate the simulation with the fixed file provided above.
I noticed tin the s10_dp_demo.v generated for the simulation the bitec_clkrec core is commented out of the code. When I uncomment it, my simulator (Aldec Active-HDL) tells me that there is no simulation data (SPD file) for this core. Does Intel provide a simulation model for the bitec_clkrec core?
Looks like you just discovered the missing sim model support.
Basically, Intel DisplayPort IP has 3rd party IP design integrated into it which is all the bitec* related design files. So, the support for it is min as this is 3rd party design where Intel also doesn't have much control over it.
Sorry and thanks for your understanding.
I am sorry.
As of now, Intel has no plan to support further sim model.
From Intel perspective, we always encourage customer to perform hardware testing on DisplayPort IP instead of running sim as DisplayPort has highly dependency on GPU selection and monitor selection.
It's safer to test with actual hardware.