We are using the HDMI core and we are getting very long lock times (one second or more). We are using a custom patch to mitigate the HDMI 2.0 mode no-internal-data-alignment issue which is still not properly documented in the core datasheet.
Could you please provide us with a documentation on how to align the incoming PHY data externally to the core (what is the required format) or provide us with a custom patch to lower the lock times? What is the lowest lock time we can expect of the core?
FAE Steve has helped you to file new IPS case 369276 for this issue and I have provided my reply in the IPS.
We can just communicate further using IPS case instead.
The Intel Premier support is no longer accessible to us, that is why I had to ask Steve for assistance. Could you please post the answer here on the forum?