We are using the HDMI core and we are getting very long lock times (one second or more). We are using a custom patch to mitigate the HDMI 2.0 mode no-internal-data-alignment issue which is still not properly documented in the core datasheet.
Could you please provide us with a documentation on how to align the incoming PHY data externally to the core (what is the required format) or provide us with a custom patch to lower the lock times? What is the lowest lock time we can expect of the core?
FAE Steve has helped you to file new IPS case 369276 for this issue and I have provided my reply in the IPS.
We can just communicate further using IPS case instead.
The Intel Premier support is no longer accessible to us, that is why I had to ask Steve for assistance. Could you please post the answer here on the forum?
- Regarding HDMI 2.0 custom patch support
- Higher lock time is expected from custom patch support that’s using the bitslip mode soft logic design
- Regarding improvement on HDMI RX lock time
- Customer can consider to use PHY alignment function that’s enabled via A10 FPGA hard PCS block in A10 HDMI example design.
- The only catch is this PHY alignment function is enabled together with transceiver data rate reconfiguration function
- From A10 HDMI example design hdmi_rx_top.v file, rx_parallel_data is generated from output of transceiver RX channel (gxb_rx) then to PHY alignment block (symbol_aligner) before it’s passed to HDMI RX core (mr_hdmi_rx_core_top)