Intel R-Tile for Compute Express Link IP fails to generate Design Example

[RicardoC]

Hi,

After configuring the Intel R-Tile for Compute Express Link IP in the Platform Designer, trying to generate the Example Design fails with:

***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries. Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
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2023.03.08.23:32:57 Warning: Both --quartus-project and --new-quartus-project switches are not used. A new Quartus project named cxl_ed will be created using the tcl script filename: /fpga/qhip4/intel_rtile_cxl_ast_0_example_design/cxl_ed.qpf.
2023.03.08.23:32:57 Info: Doing: qsys-script --pro --script=cxl_ed.tcl
2023.03.08.23:33:02 Info: set_project_property DEVICE_FAMILY Agilex
2023.03.08.23:33:02 Info: set_project_property DEVICE AGIB027R29A1E2VR0
2023.03.08.23:33:02 Info: add_instance dut intel_rtile_cxl_ast
Internal Error: Sub-system: DEV, File: /quartus/ddb/dev/dev_family_info_mgr_body.cpp, Line: 389
(part < DEV_PART_GENERIC) && (part > DEV_PART_INVALID)
Stack Trace:
Quartus 0xc5be0: DEV_FAMILY_INFO_MGR_BODY::get_lite_desc_of(DEV_PART_ENUM) [clone .cold] + 0x3e (ddb_dev)
Quartus 0x13e230: DEV_PART_MANAGER::get_device_of(DEV_PART_ENUM) const + 0x10 (ddb_dev)
Quartus 0x2ac0b: LAMPAS::load_lampas_definition_for_part(DEV_PART_ENUM, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0xbb (db_lampas)
Quartus 0x113e8: lampas_load_lampas_definition_for_device + 0x122 (db_lampas_tcl_impl)
Quartus 0x50fb7: TclNRRunCallbacks + 0x47 (tcl8.6)
Quartus 0x527df: TclEvalEx + 0x94f (tcl8.6)
Quartus 0x52ad6: Tcl_EvalEx + 0x16 (tcl8.6)
Quartus 0x52afd: Tcl_Eval + 0x1d (tcl8.6)
Quartus 0x3013: Java_com_altera_tcl_interpreter_NativeTclWrapper_eval1 + 0x76 (qsys_tcl_jni_bridge)
Other 0x7f46709bdfc7:
Other 0x7f46709add80:
Other 0x7f46709add80:
Other 0x7f46709adffd:
Other 0x7f46709adffd:
Other 0x7f46709ae042:
Other 0x7f46709ae042:
Other 0x7f46709ae042:
Other 0x7f46709adffd:
Other 0x7f46709ae042:
Other 0x7f46709a64e7:
Quartus 0x69ab62: JavaCalls::call_helper(JavaValue*, methodHandle*, JavaCallArguments*, Thread*) + 0xe32 (jvm)
Quartus 0x698173: JavaCalls::call_virtual(JavaValue*, KlassHandle, Symbol*, Symbol*, JavaCallArguments*, Thread*) + 0x263 (jvm)
Quartus 0x698777: JavaCalls::call_virtual(JavaValue*, Handle, KlassHandle, Symbol*, Symbol*, Thread*) + 0x57 (jvm)
Quartus 0x73c7dc: thread_entry(JavaThread*, Thread*) + 0x6c (jvm)
Quartus 0xad8d87: JavaThread::thread_main_inner() + 0x1c7 (jvm)
Quartus 0xada13a: JavaThread::run() + 0x2fa (jvm)
Quartus 0x966a92: java_start(Thread*) + 0x102 (jvm)
System 0x7ea5: start_thread + 0xc5 (pthread)
System 0xfeb0d: clone + 0x6d (c)

End-trace

Any suggestions?

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

May I know if you have CXL IP License? If yes, may I know what is the setting that you used for me to duplicate the issue? Do you follow the CXL IP Design Example user guide?

[RicardoC]

Hi,

Yes, we do have the CXL IP License.

The CXL IP Design Example uses the RTile Intel FPGA IP for Compute Express Link (CXL), but the question was related to  Intel R-Tile for Compute Express Link IP. Therefore, I cannot follow the user guide.

Ricardo.

[JohnT_Intel]

Hi,

Can you provide me the step for me to duplicate the issue? I am not able to observed the issue from my side.

[RicardoC]

Sure, John.

1. Create a new project for the "Agilex I-Series with HPS only".

2. Create a new system in Platform Designer and add the "Intel R-Tile for Compute Express Link IP" to it. Press the button "Generate Example Design".

Thanks,

Ricardo.

[JohnT_Intel]

Hi,

Please use "R-tile Intel FPGA for Compute Express Link" IP to generate the design example.

[JohnT_Intel]

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