Interlaken Metaframe start signal in Stratix V 10G PCS

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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Interlaken Metaframe start signal in Stratix V 10G PCS

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I want to measure the delay between the transmitter and receiver of an interlaken connection as precisely as possible. In order to achieve that I want to use the start of the Interlaken metaframe as a reference.

Is there an output signal available (and accessible by the FPGA core logic) in the 10G PCS hard IP of Stratix V which indicates the start of the Interlaken metaframe? I would need such a signal (or any equivalent signal) for both receive and transmit side.

Any help would be appreciated.

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