FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6486 Discussions

Interlaken Metaframe start signal in Stratix V 10G PCS

Altera_Forum
Honored Contributor II
1,002 Views

I want to measure the delay between the transmitter and receiver of an interlaken connection as precisely as possible. In order to achieve that I want to use the start of the Interlaken metaframe as a reference. 

Is there an output signal available (and accessible by the FPGA core logic) in the 10G PCS hard IP of Stratix V which indicates the start of the Interlaken metaframe? I would need such a signal (or any equivalent signal) for both receive and transmit side. 

 

Any help would be appreciated.
0 Kudos
0 Replies
Reply