I want to measure the delay between the transmitter and receiver of an interlaken connection as precisely as possible. In order to achieve that I want to use the start of the Interlaken metaframe as a reference.
Is there an output signal available (and accessible by the FPGA core logic) in the 10G PCS hard IP of Stratix V which indicates the start of the Interlaken metaframe? I would need such a signal (or any equivalent signal) for both receive and transmit side.
Any help would be appreciated.
