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Altera_Forum
Honored Contributor I
987 Views

Internal memory usage using MegaWizard RAM: 2-port

Hi, 

 

I am using 8k, 8-bit wide internal 2-port RAM. Here's the instantiation in Verilog: 

working_ram ram_test 

.data(ram_data_test), // input [7:0] data; 

.rdaddress(ram_rd_addr_test), // input [12:0] rdaddress; 

.rdclock(module_clk), // input rdclock; clk_ftdi now, will be different later.  

.wraddress(ram_wr_addr_test), // input [12:0] wraddress; 

.wrclock(module_clk), // input wrclock; 

.wren(ram_wren_test), // input wren; 

.q(ram_output_test) // output [7:0] q; 

); 

 

module_clk is 120 MHz. I am writing by asserting ram_wren_test and presenting it with appropriate ram_data_test and ram_wr_addr_test. However, when I try to readback by presenting it with same sequence of addresses on ram_rd_addr_test, the readback values (ram_output_test) are all 0s. Everything is @ posedge.  

 

Signaltap timing looks good. None of the ports are connected to any pins as this is for internal logic/storage only. The instantiation is not at top level, rather one level below it. Is the compiler optimizing out anything here? Or is there anything I'm missing in setup/settings?  

 

If there is a link to sample verilog code or timing on how to use internal RAM, it would be very helpful. Altera doc on RAM/ROM has a link to some .zip file which has few verilog examples , but the link is dead.  

 

thanks, 

swguy
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6 Replies
Altera_Forum
Honored Contributor I
39 Views

Are you sure you don't write and read same address at same time?

Altera_Forum
Honored Contributor I
39 Views

 

--- Quote Start ---  

Are you sure you don't write and read same address at same time? 

--- Quote End ---  

 

 

yes, I checked: read only happens after write is complete. I also changed the IP to have read_enable and tried again; but same issue.  

thanks,
Altera_Forum
Honored Contributor I
39 Views

I don't have any issue with Dual Port Ram. Could you post .qar project?

Altera_Forum
Honored Contributor I
39 Views

Hi, Unable to share code due to work policy, but 3 images from signaltap are attached in zip. First image has the entire write-then-read op and next two have the zoomed in view of Wr and Rd, respectively. thanks for quick responses...

Altera_Forum
Honored Contributor I
39 Views

Do you have read clock right?

Altera_Forum
Honored Contributor I
39 Views

yeah, forgot to mention that although I've separate rd and wr clks, for testing I'm using same module_test_clk for rd and wr.

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