FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

Inverted clock for flipFlop in dsp builder

Altera_Forum
Honored Contributor II
814 Views

Hi, 

 

I am implementing a MAxPlus project in DSp-Builder. 

 

2) In one part of circuit the clock input of the FlipFlop is inverted using an inverter. how I can implement this in DSP-builder? 

 

3) If i try to use HDL import it gives error of Multiple clock due to same above reason. Any idea how to fix this issue? 

 

kind Regards 

Hamid jabbar
0 Kudos
0 Replies
Reply