Ip megafunction license

Altera_Forum · ‎10-22-2009

I have Quartus II, i have installed the evaluation trial 30 days.

But in my project there are limitations with eda netlist generation and

the pof file for the programmation of the FPGA (DE2 ALTERA CYCLONE II).

There are many errors when i compile the project like

open core plus time limited file etc...

Maybe i must insert the file of the license trial somewhere?

Can someone help me?

I must implement sdram with Sopc builder but i can't do it with this errors.

Thanks.

Altera_Forum · ‎10-22-2009

"open core plus time limited" is not an error, it is just informational that you do not have a valid license and therefor can't produce files that can be used for production purposes.

you can test and run your application as long as there is a connection between quartus and your fpga. maybe via your usb blaster. it is possible to cheat a bit and let the target fpga run up to 1 hour without a connection between quartus and fpga.

if you enable 30day trial, there is no license file needed

so it is normal that you won't be able to produce all the netlists or some output files. thats available with a valid license file.

(this behavioral is very common, lots of other software act like this, you can almost do everything except of saving or printing)

you can create a complete nios II project with all the sopc features, but you won't be able to create a file you can use to programm epcs or cfi to get a system that runs imediatly after power on. you need a valid license for this.

Altera_Forum · ‎10-22-2009

Thanks you for the answer.

Do you know if it's simple to implement the sdram or the flash memory without the use of open core plus or sopc builder?

So i can't do it without the specific license.

Thank you!!

Altera_Forum · ‎10-22-2009

the flash memory is a straight foreward memory, the ip itself is just a wrapper from external memory to the internal avalon bus.

for the sdram you need an ip that does the refresh as well as the fsm for accessing sdram. have a look at opencores.org there is one pretty simple sdram ip used at the zet project.

Altera_Forum · ‎10-22-2009

so, you say that for the flash memory i can only create an entity in my project and assign directly the pin of my board to this entity?

The problem, in this case, is the clock pin that there isn't in the datasheet or de2 user manual of my board.

There are only Address Pins, Data Pins,Chip Enable,Reset and Write Enable.

Is it possible? Maybe is the clock fixed and internal?

Altera_Forum · ‎10-22-2009

you need to look at the schematics of your board what is also connected to that tristate bus.

if you only want to use the cfi flash then you can directly connect your ip to that memory and set all other signals to disabled for those other components that are also connected to that bus.

a cfi flash memory has no clock pin.

Altera_Forum · ‎10-22-2009

Sorry for this last question.

Using the sopc builder to implement the cfi flash there are the problems with open core plus license.

Do you know if there is a guide to implement flash memory S29AL032D in my vhdl design without using the sopc builder ?

Thank you!

If there is a vhdl example for me it will be the best way.

Thank you!!!

Altera_Forum · ‎10-22-2009

sorry i have no guide for you, but cfi memory is like accessing any other tri stated memory or device. like sram or a axternal uart, pio ...

don't worry that you try to access a cfi flash, just think it is just an external memory.

you need adr line,

data in and out bring them together as inout / bidir ..

and of course chip select and read/write control

you need a fsm that controls your access state (setup, access, hold) so that you enshure you meet the timing.

that is realy pretty straight foreward...

Altera_Forum · ‎10-22-2009

thank you very very much!!!