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Is DDR2 bursting?

Altera_Forum
Honored Contributor II
850 Views

Hi, 

 

Thanks for your answers. I could do the user controlled refresh on DDR2. But, now struck with another problem.  

 

We know that DDR memories work in a burst fashion. To describe in detail, check my settings in the images attached. 

 

1) I use the same data bit width, 32, for DDR2 HPC II local interface as well as the master connected to it.  

2) In the full rate mode both operate at the same frequency of 125 MHz. 

3) Number of DQs = 16. "memory Burst Length = 4" and "Maximum Local Interface Burst = 8". 

4) You can see in the image SOPC.bmp that I try to access the DDR2 from a component called tt_shared_ddr2. The component simply connects the instruction and data cache of the CPU (32 byte cache line, 32 byte burst) to the DDR2. 

5) For each "cache miss" burst of 8 is asked to the tt_shared_ddr2, which is simply forwarded to the DDR2. 

6) I tried both address mapings "chip-bank-row-col" and "chip-row-bank-col". 

 

now my question: 

 

When the data is asked in a burst fashion, the responce is only word by word. And there are >32 clock cycles between two "read_data_valid". 

 

According to the documentation, 16 bit DQs * 4 Beat burst = 64 bits of data. And that makes 2 "read_data_valid" back-to-back. I am using cyclone III development kit. 

 

Best regards, 

Hardik Shah
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Altera_Forum
Honored Contributor II
103 Views

Small clrearification, 

 

I checked in signal tap II logic analyzer that "read_data_valid" signal stays high once per 34 clock cycles for a read operation.  

 

1) The module "tt_sahred_ddr2" sets the burst_count to 8. 

but 

2) local_size[6 downto 0] = 1. local_burstbegin is as expected. 

 

(Note: I increased the "Maximum Local Interface Burst" to 64 now and hence local_size is 7 bits wide now.) Kindly, check the settings in the attached ZIP file and help me. 

 

Thanks and best regards, 

Hardik Shah
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