Is it allowed to connect two pll inclk0 to the same input clock ?

[ADufl]

Hi,

I have a design on a EP4CE40 FPGA where I instantiated a second pll and mapped the inclk0 input to the same input clock as the first one. I get a Critical Warning (176598): PLL "pll3:inst_pll2|altpll:altpll_component|pll3_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2".

Knowing that the input clock is connected on T1/T2 differential clock pin (DIFFCLK_1p and DIFFCLK_1n). Is it not allowed to connect two pll IPs to the same input clock ?

Thank you.

[ADufl]

Yes. I will provide such design next week.

Thank you.

[Rahul_S_Intel1]

Hi ,

Kindly find the log message as attached ,I could not able to find any warning on the above project compilation , let me know if I am missing some thing.

Quartus version 18.1

[ADufl]

Line 578 :

Critical Warning (176598): PLL "pll:inst_pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_T2"

[Rahul_S_Intel1 · Accepted solution]

Hi ,

I done the below analysis from my side to debug the issue .

1. Remove the pin constraints from the assignment editor , to isolate any pin mapping issue : But I found warning is present
2. Analyzed the PLL logic in the design and found that same clock is been connected to to two pll by using altclkctrl
   1. The out put frequency from two pll, not allowing to merge together
   2. So the input pin for the both pll is same , that makes the quartus to assign two different pll one is near to the input pin other little bit far as there is no pll available neart to the input pin .
   3. This makes the reason for the warning .
3. And also I am kindly requesting to check the timing of the design

[ADufl]

Thank you for your support, your last message answers my question. 

[Rahul_S_Intel1]

Hi ,

With the above support ,May I close the thread

[ADufl]

Yes you can.

Thank you.