I was wondering if it is possible to monitor LTSSM signals on TEST_OUT bus. I am using a Cyclone IV GX Transceiver starter kit provided by Altera and have parametrized a PCIe Hard IP in QSYS. I am following the the reference design sample, which as I can see TEST_IN bus is initialized and then TEST_OUT bus is polled to detect L0 state as below:
assign test_in[30 : 32] = 0;
assign test_in[31 : 9] = 0;
assign test_in[4 : 0] = 4'b0101;
assign test_in[4 : 0] = 5'b01000;
L0_led <= ~(test_out_icm[4:0] == 5'b01111)
but when i am trying this (I am tapping LTSSM and TEST_OUT on SignalTap), i can not find any correlation between TEST_OUT and LTSSM signals.
LTSSM signal reaches to L0 (5'b01111) and remains stable but TEST_OUT is switching between
Any comment is appreciated. Thanks.
Thanks for your comments.
But what I get from the reference example provided for Cyclone IV GX Tranceiver Starter kit, it polls test_out[4:0] to detect the transition to L0 state (0x0f). How we can explain this?
I am sorry to said that CIV is a legacy device and we do not have details information about it. What I say here is follow the document, the test_out is for pipe status signal and my understand is these signal is used for internal debug previously. If you want to know the LTSSM, I will suggest you monitor the LTSSM signal directly.