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Altera_Forum
Honored Contributor I
1,632 Views

Is it save to use the PIO in QSYS

Hello, 

 

I have several PIOs in my QSYS design to communicate with some of my own designed IPs. 

My IPs mostly use other clock signals than the PCIe-Clock and are therefore not synchronized to the clock of the PIOs. 

For example I have an Pulsecounter with only one 1-Bit-Input and a 32-Bit-Output which is read out by an 32-Bit PIO. 

I think I don't have to explain, what this Pulsecounter does. 

 

I ran a test with a similar IP, which switched fast between two known values. Then I read out the values as fast as I could from the PIO. I read 25Bil. values, but none was corrupt. I wonder how this is achieved especially because the PIO has no Input-Clock or something like that. 

 

My questions are: 

Is it save to read from the PIO while the Pulsecounter changes its output? Or may it be that I read some Bits with the old value and some bits with the updated value? How does Altera achieve such a reliability without a clock or a "valid"-Signal or something else? 

 

Yours 

 

Steffen
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11 Replies
Altera_Forum
Honored Contributor I
34 Views

 

--- Quote Start ---  

My IPs mostly use other clock signals than the PCIe-Clock and are therefore not synchronized to the clock of the PIOs. 

--- Quote End ---  

 

 

Does it mean that your IP Clock and PIO clock are different? If this is the case then you should use Avalon Clock Crossing Bridge for synchronization. 

 

 

--- Quote Start ---  

My IPs mostly use other clock signals than the PCIe-Clock and are therefore not synchronized to the clock of the PIOs. 

--- Quote End ---  

 

 

Is it save to read from the PIO while the Pulsecounter changes its output? 

 

Off course it is safe to use PIO. To read from the PIO or to write the PIO is managed by Altera.You can consider that PIO is nothing but the IP like other IP provided by Altera. So when you read from the PIO,Avalon Master generates read request and address of PIO.PIO returns Pulsecounter data (value of pulse counter at the time of read request generated by Avalon Master) on Avalon data bus. 

 

I hope, I have cleared your doubt.
Altera_Forum
Honored Contributor I
34 Views

No, that doesn't clear my doubt.  

 

As you said: The PIO returns Pulsecounter data at the time of read request generated by Avalon Master. What if the Pulsecounter changes its value exactly the same time? 

For example it changes from "01" to "10". If there is a little skew between the two bits, nearly every combination ("00", "11") is also possible to be seen by the PIO for a very short time. If the PIO samples the Data in this little piece of time, the Data should be corrupt. But I have never seen them corrupt. This is nice, but WHY? 

 

I don't see how I should insert a Clock Crossing Bridge here. The PIO has no additional clock port and some of my other IPs are working asynchronously. So I can't predict when the Data are changing and when they are valid.
Altera_Forum
Honored Contributor I
34 Views

Your are right.If PIO and IP Clocks are different then there may be a chance that system goes into the metastable state. 

 

But I don't understand the reason for using different clock for Pulsecounter and PIO.I think you can use the same clock for both Pulsecounter and PIO and can use Avalon Clock Crossing Bridge between Avalon Master and PIO if your Avalon Master is running at frequency other then PIO frequency.
Altera_Forum
Honored Contributor I
34 Views

The Pulsecounter doesn't have a clock! It just counts pulses asynchronously.

Altera_Forum
Honored Contributor I
34 Views

I believe that one pulse or signal is input of the Pulsecounter module and based on this signal or pulse you are incrementing the counter.I think it will either generate latch or combination loop. Both can cause significant stability and reliability problems in design.I am sure that Quartus Design Assistant will report violation for your Pulsecounter design. So my suggestion is to try some other alternative.

Altera_Forum
Honored Contributor I
34 Views

No, there is not a single Warning about my Pulsecounter, everything works just fine. I use the rising_edge on the Input to Increment the Output-Signal. That's all. I even don't see a chance for any loop. It's just like "If (rising_edge(Input)) then (Output + 1) else (Output)". Sorry to disappoint you. 

 

Hmm, perhaps they are using an attribute like 'STABLE or 'STABLE(t) on the Inputs to ensure the data will not be read during changing.
Altera_Forum
Honored Contributor I
34 Views

Firstly counting pulses asynchronously is a bad idea. You should synchonise the pulse to a clock and then count the transitions on the next clcok edge. 

 

Secondly data is moved between clock domains it must be put through a multi-stage synchroniser. Qsys will add one (transparantly) between avalon masters and slave. 

 

Thirdly any such synchroniser can only synchronise a single bit - you cannot move the output of a ripple counter between clock domains. 

So you either need to count in grey binary, or just transfer the LSB and count in the target domain.
Altera_Forum
Honored Contributor I
34 Views

OK, I see the discussion leads to a wrong direction: 

My question was NOT about "How to implement an IP which counts Pulses". 

 

I asked "Is it save to use PIOs? So let's get back to that now. Is it possible that a Altera PIO can read in values which are currently changing. 

I made a testdesign which switches rapidly between two values (0xAAAAAAAA and 0x55555555) and I read them out via "PIO -> Avalon -> PCIe" as fast as I can. 

But since I started my testsoftware, there were NEVER a corrupt Value like 0xAAAAFAAA or 0x55155555. 

This lets me think that the Values on the PIOs are reliable. BUT WHY? Does Altera make sure somehow that no Data are read in which are currently changing? 

 

Since now I read the PIO about 40 Billon times and there was never a failure in the Datas (Great!!!!). BUT WHY?
Altera_Forum
Honored Contributor I
34 Views

Hi Steffen, 

 

If your test source was a register actually hard coded to make either 0xAA..AA or 0x55..55 it seems possible that Quartus has implemented it as just a pair of wires carrying '1' or '0' connected to all the PIO inputs. It may even be a single wire with a toggling signal, with inverters built into alternate PIO outputs. The time differences involved to each bit might then be in the psec region, so the chance of a transition event would be pretty small. Beware of optimisations. I think your test needs more randomness to check for safety of the readings. 

 

 

Regards, 

Simon
Altera_Forum
Honored Contributor I
34 Views

Actually I use a Output PIO to set a value via Software. This Output is routed to my IP which inverts the Value when the clock is high, and doesn't invert the value when the clock is low. Then the inverted/not inverted Output is wired to a PIO as Input. 

Therefore the Compiler can't know which value I want to invert/not invert because it is not hard coded.
Altera_Forum
Honored Contributor I
34 Views

Maybe the logic paths of the inverts are close enough that getting a different value is extremely unlikely. 

Try counting clocks and looking for a jump backwards.
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