We have a A10 design which need to support 10GE + 1588V2 feature. We have checked user guide named " ug-20016—Low Latency Ethernet 10G MAC User guide.pdf " -> “ 3. 1G/10G Ethernet Design Example for Intel Arria 10 ", its clock scheme show as below pic .
We have two questions regarding of those three "input clocks"
a) pll_ref_clk_10g[n] 644.53125 MHz
b) pll_ref_clk_1g[n] 125 MHz
c) mm_clk 125 MHz
(1) Since we only need support 10GE, not 1G required, I guess we need "pll_ref_clk_10g[n] 644.53125 MHz" clk, while we can remove " b) pll_ref_clk_1g[n] 125 MHz " clk. Is that correct ?
(2) Regarding of "1588V2" Feature, is " c) mm_clk 125 MHz " is mandatory ? Can we change the mmclk from "125MHz " to our on-borad "100Mhz" clk ? I mean is this "125MHz" is a mandatory requirement clock frequency ,or it can be changed to other frequency clocks, such as 100Mhz, or so ?
// Thanks & best regards
Pls see my reply below.