We have a A10 design which need to support 10GE + 1588V2 feature. We have checked user guide named " ug-20016—Low Latency Ethernet 10G MAC User guide.pdf " -> “ 3. 1G/10G Ethernet Design Example for Intel Arria 10 ", its clock scheme show as below pic .
We have two questions regarding of those three "input clocks"
a) pll_ref_clk_10g[n] 644.53125 MHz
b) pll_ref_clk_1g[n] 125 MHz
c) mm_clk 125 MHz
(1) Since we only need support 10GE, not 1G required, I guess we need "pll_ref_clk_10g[n] 644.53125 MHz" clk, while we can remove " b) pll_ref_clk_1g[n] 125 MHz " clk. Is that correct ?
(2) Regarding of "1588V2" Feature, is " c) mm_clk 125 MHz " is mandatory ? Can we change the mmclk from "125MHz " to our on-borad "100Mhz" clk ? I mean is this "125MHz" is a mandatory requirement clock frequency ,or it can be changed to other frequency clocks, such as 100Mhz, or so ?
// Thanks & best regards
Pls see my reply below.
- Can you skip usage of pll_ref_clk_1g ?
- If you look back at the diagram (orange colour clock path), pll_ref_clk_1g is not only used to clock fPLL for 1G operation but also is used for 1588 design block like TOD, TOD synn. Therefore, it's not recommended to skip the usage of this clock
- Anyhow, It's always a good design practice to supply all the required clock to IP design be it whether you want to use certain feature or not to ensure all IP functionality is working correctly.
- I can't tell for sure whether the clock will be used to clock some internal design logic insides IP design or not
- Can you use lower frequency of mm_clk like 100MHz ?
- Again, mm_clk is used to clock multiple design block as well as shown in green colour clock path
- For csr_clk and mgmt_clk, it's fine to lower down the clock frequency to 100MHz but 1588 design block required 125MHz.
- To be safe, pls stick to 125MHz clock frequency as per example design guideline