FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

Is "data valid" signal required for the clocked video input?

Altera_Forum
Honored Contributor II
‎03-07-2010 09:37 PM
1,209 Views

Hello. I'm a video newbie trying to use the clocked video input with a DE2-70 dev board from Terasic, which includes the ADV7180 video decoder chip. My current processing chain includes several other VIP blocks, ending with a clocked video output driving a VGA port. 

 

The problem is that the ADV7180 doesn't have a "data valid" output signal, so I'm not sure what to do with the CVI's vid_data_valid_to_the_alt_vip_cti_0 input. I assume that signal is used to indicate blanking intervals, but I'm not sure why it's needed since I configured the CVI to use embedded sync codes. Do I need to derive my own data valid signal? 

 

Just as an experiment, I have the signal tied high, but I'm not getting output on my monitor. There are probably problems with how I have the other VIP blocks configured, but before proceeding I wanted to check my 

understanding of the "valid data" input to the CVI. 

 

Any information would be appreciated!
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎03-07-2010 11:16 PM
296 Views

Somehow I missed the blurb in the documentation about vid_datavalid behaving "slightly differently" for embedded sync signals.  

 

It seems that the right thing to do would be to simply tie the signal high; is that correct? (Assuming that the ADV7180 delivers one sample per clock.)
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-09-2010 09:49 AM
296 Views

Data valid is used in cases that the video input has some times intervals with null data (not active data, not blanking data and not SAV or EAV, just stuffing).  

In the case of the ADV7180 it is not relevant and as you understand correctly just tie it to VCC.
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.