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5746 Discussions

Is there a 10GBASE-R with 1588 reference design for Stratix 10 L/H Tile Transceiver?

SThom66
Beginner
588 Views

There is conflicting documentation regarding whether 10GBASE-R can use 1588v2. I would like to see a reference design that supports this application.

 

I looked at Application Note AN-849 which discusses a 10GBASE-R reference design with 1588v2 support using the L/H Tile transceiver and Low Latency 10G MAC. However, once you click the "Enable 10GBASE-R register mode" checkbox in the MAC component, as it states in the application note, the 1588 Timestamp option turns grey and cannot be selected.

 

The AN-849 application note also points to a Low Latency Ethernet 10G MAC example design UG-20073. In section 5 of this user guide there is a reference design for a MAC that uses the 1G/2.5G/5G/10G Multi-rate PHY not the H/L Tile transceiver. Also, this example is not for 10GBASE-R. Section 2 of the user guide has a 10GBASE-R design example but it does not use 1588v2.

 

Is there a problem with 10GBASE-R and 1588v2 support?

 

 

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7 Replies
Deshi_Intel
Moderator
556 Views

Hi,

 

Sorry for the confusion on AN849. This reference design is not meant to showcase 1588 functionality but rather focus more to showcase the low latency achievement.

 

For the LL 10G MAC - yes, PTP 1599 options will be disabled once 10GBASE-R register mode is turned on.

 

For 10GBASE-R 1588 reference design, I would recommend you to generate it using LL 10G MAC IP + Multirate PHY IP. Attached is the screenshot of selecting the preset in LL 10G MAC IP.

 

The 10G protocol support in Multirate PHY IP is actually 10GBASE-R as show in another screenshot below.

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
556 Views

The 10G protocol support in Multirate PHY IP is actually 10GBASE-R as show in attached pic.

SThom66
Beginner
542 Views

The Multirate PHY requires a license whereas the L-Tile Native PHY does not. Therefore, I would like to know how to connect the Native PHY.

I read through the L-tile PHY user guide section 2.4.3 explaining the latency pulses. It shows that a latency calculation IP block is required to determine the total latency. How would this be used in a 1588 design? The MAC has a tx_path_delay and rx_path_delay inputs that usually come from the PHY. Would path delay inputs now need to be generated from the pulses? How is this accomplished?

Deshi_Intel
Moderator
529 Views

Hi,

Unfortunately I won't be able to advise on the 1588 solution build with NativePHY IP as it's not part of solution package offered by Intel FPGA.

As you are aware, the 1588 feature support is available in Multirate-PHY IP. 

So, it's a fair trade here. Either user pay for the solution or develop the solution by themselves.

Thanks.

Regards,

dlim

 

 

       

 

SThom66
Beginner
519 Views

OK.

Can you tell me if the example design implements the full PTP protocol stack? In other words, does it implement the Best Master Clock Algorithm, PTP state machine, etc? I am wondering if I can use the bulk of the example design in a project without much CPU interaction. 

I can see in the simulation that it is sending some PTP SYNC and DELAY REQUEST packets but I don't see the TOD clocks being updated.

Thanks.

Deshi_Intel
Moderator
432 Views

Hi,


Sorry for the late respond as I was waiting for Intel internal team to publish another 1588 reference design to better answer your questions here.


For below S10 1588 design example


For below latest S10 1588 reference design (that just got published last week)


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
390 Views

HI,


I have not hear back from you for few weeks.


I hope the latest reference design sharing on Aug 17 help to clear you doubt.


For now, I am setting this case to closure.


Thanks.


Regards,

dlim


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