Is there a way for CvP over PCIe to do CvP update?

[HTong1]

Reading the CvP over PCIe, it looks like Intel has moved away from CvP Update Mode for all PCIe Gen3 IP and the Arria 10 does not support CvP Update at all for any PCIe Gen. Is there a way to use the Arria 10's CvP over PCIe Initialization to do CvP Update? Arria 10 documents states that instead of CvP Update, Partial Reconfiguration over PCIe should be used. But PR is much harder to do than CvP Update because PR requires partition and lock of region(s) but CvP Update does not. If there is no way for Arria 10 to do CvP Update, does Intel have any plan to bring back CvP Update to any device or any gen of PCIe? Thanks.​

[JohnT_Intel]

Hi, There is no plan to have CvP update to Arria 10 and newer device.

[HTong1]

​Hi, we just found that on page 6 of the "Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide" (ug-s10-cvp-18-0.pdf), the Cvp Update is supported on Stratix 10 devices, so would like to request that Intel answers the following two questions:

1. Would Intel please confirm that Stratix 10 does support CvP Update?
2. If Status 10 does support CvP Update, why can Arria 10 not support CvP Update?

The reason to ask the above  questions is that it is confusing why Stratix 10 supports CvP Update but Arria 10 does not and even there is no plan for future Arria 10 to support CvP Update. Are they using different PCIe IP from different third party developers?

Thanks

[JohnT_Intel]

Hi, Sorry for my mistake. Yes, Stratix 10 do support CvP update. The reason that CvP update is not supported in Arria 10 is due to the architecture implementation

[HTong1]

​Hi,

By reading thru the ug-s10-cvp.pdf, it appears that the Stratix 10's so-called CvP Update is very similar to Arria 10's Partial Reconfiugation in the way that it requres physically partitioning and locking a region, in this case, the so-called "core region". The only difference is that it appears that it does not require manually instantiating PR controller and PR region controller. The true CvP Update mode that existed in eariler devices that does not require physically partioning and locking any region no longer exist in Stratix 10. Can Intel clarify what is going with Stratix 10's CvP Update? If the ug-s10-cvp.pdf is correct, the Stratix 10's CvP Update mode is not as robust or flexible as Arria 10's Partial Reconfuration that allows precise control of start and stop of PR and as well as multi-region PR. In Intel's product road map, except device size, is Arria 10 more advanced in Intel's device development (it looks like Arria 10's PR is more advanced that Stratix 10's CvP Update that is a shrunk version of PR)? Does Stratix 10 support Partial Reconfiguraton (essentially the question may be equivalent to "Does Stratix 10 have PR controller and PR region controller)? Thanks.  

[JohnT_Intel]

Hi, Yes, it is a bit similar but the difference is that the CvP update will need to split between periphery and core design while PR can split the core design into several partition. So for CvP update mode, it will update the whole core region. This features will be similar to Stratix V CvP update mode. Stratix 10 also support PR where it will be the same implementation as Arria 10.

[HTong1]

​Hi, is there any plan that the true CvP Update (does not require physically partitioning and locking a region for the entire core design) will be available to Stratix 10 in the near future? The reason to ask this is that the CvP Update in Stratix 10 today is equivalent to PR when PR split the periphery and core design so that the periphery becomes a static region and the core design becomes a persona, which means that CvP Update of Statix 10 is essentially one of many ways of PR. Thanks.

[JohnT_Intel]

Hi, This is the only way that has always been use even in V series device. The reason that we need to split the partition between the core and periphery is so that you are able to just recompile the core partition without impacting the periphery design. If this is not being performed then CvP will not work as user might be accidentally make changes on the periphery image where it will impact the CvP update.

[HTong1]

​Hi, it is understood that both V and 10 series require logic partition between periphery and core. But the V series document ug_cvp.pdf never mentions a requirement to physically partition and lock the core region. The main disadvantage of the Stratix 10's CvP is that it requires physically partition and lock the core region (aka, place and route). Unless the V series ug_cvp.pdf document is incorrect, the CvP Updates between V series and 10 series are different. V series CvP Update is similar to CvP Initialization while 10 series CvP Update is actually a subset of PR. Looks like even though V series document clearly states that CvP Update feature will be gone, another Intel team developing 10 series mistakenly used the term CvP Update for what is actually a PR with automatic (transparent) insertion of PR controllers and with limitation of what the "persona" should be.

[JohnT_Intel]

Hi, If you look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_cvp.pdf Chapter 4, it is mention that the design is split into 2 partition.

[HTong1]

​Yes, but these 2 partitions are only logic partitions. The ug_cvp.pdf never mentions any physical partition requirement, which is a big difference. That said, if ug_cvp.pdf document is defective in the way that it mistakenly omits the physical partition requirement, then Intel may have never supported true CvP Update. What is documented in ug_s10_cvp.pdf is the same as the PR thru PCIe in Arria 10 except that s10 does not require insertion of PR controllers, both requires physical partition, which is bad.

[JohnT_Intel]

If you look carefully on ug_cvp.pdf file it is using the same method as the S10 CvP update. The reason that it need a physical partition in order for Quartus to split the design optimization correctly where the periphery region is not being accidentally modified.

[HTong1]

Hi, on page 36 of the ug-s10-cvp.pdf the Figure 16 and Figure 17 shows the requirement to create Logic Lock Region and lock the region with the origin, width, and height for physical placement. However, ug-cvp.pdf does not use Logic Lock Region and shows nothing to specify the region’s origin/width/height. Instead, ug-cvp.pdf uses “Design Partition”, which is a different menu item below the “Logic Lock Region” item. The ug-cvp.pdf specifies two regions at first: periphery region and core region, then it further divides the core region down to static region and reconfigurable region, and only the reconfigurable region needs to be designated as a Design Partition with multi-persona capability. If ug-cvp.pdf does not omit anything in the document, its advantage is that it does not require user to specify the region with origin, width, and height. In other words, Quartus handles the regions sizing and placement by itself. In ug-s10-cvp.pdf, the sizing and placement of the region has to be done by users. The ug-cvp.pdf I downloaded is UG-01101 dated 2016.10.31. Does Intel have a newer version of the ug-cvp.pdf that is updated to change the way how its Cvp Update is done?

[JohnT_Intel]

Hi, I understand your concern. There is some changes on the tools where Stratix 10 is using Quartus Prime Pro edition and we have enhanced that you can reserved some of the core partition or lock the logic in certain region where in each CvP revision, this location will not be changed. But when you performed CvP update, the whole core region will be reconfigured. This new features is only help in Stratix 10 CvP design is for user to fixed certain location and design. This core split partition and logic lock is optional where user can also not include if there does not want to retain the module design.