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Issue about DMA Read with PCIe Hard IP (for ARRIA10) in simulation

Altera_Forum
Honored Contributor II
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Hi, 

 

I'm working on PCI Express Hard IP (lane x1, gen2 for ARRIA10). To check my design, I don't use ALTERA BFM but an other solution. Write and Read access from RC to application are ok, DMA write access (from application to RC) are ok but read DMA access failed. ALTERA provide a monitor to check access and in the log file, I can see my DMA read access is transmitted and a completion is coming from hostmemory but I have nothing on my RX AVALONST interface. So the EP has the packet for sur but it's not delivered via the bus to the application. All my inputs seem to be the same as example design testbench... I assert cpl_pending when EP is waiting for a completion and increment my tx_credit_fc_sel to allow an output completion... Should I do some special access before DMA read access? Or should I reconfigure my PCIe Hard IP? 

I am looking for a solution... 

 

Thank you for your help.
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