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Altera_Forum
Honored Contributor I
1,896 Views

Issue with 245 Fifo sync mode

Dear All, 

 

I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the sent data to PC. 

 

 

I am using the 245 fifo sync mode. 

 

All is working fine, expect that I rarely have a lose of one byte that appears randomly. 

 

So for example, when I send a packet of 512byte, i received well the 512byte but when I repeat this operations 200 times, I noticed that sometimes I only receive 511 byte and when I check where happens the lost byte, it happens randomly. And when I send a packet of 65.536 byte, again sometimes, I only received 65 535 byte. 

 

The strange thing is that when a lose occurs, this is always one byte. 

 

Can anyone help out me there to solve this problem ? 

 

Attached you will find my VHDL code. 

 

Thank you for your help !
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10 Replies
Altera_Forum
Honored Contributor I
63 Views

Do you have timing specs for the design? are they correct? Does the design meet timing? 

Are all the signals in your design synchronous to "clk"? if they are not, have they been synchronised correctly? 

 

Your description sounds like a timing problem.
Altera_Forum
Honored Contributor I
63 Views

Thank you for your answer. 

 

I checked and, yes, all the timing specs are met and all the signals are synchronized to the clock (60 MHz) delivered by the FT2232H chip. 

 

From what I have observed, the lost byte does not occur in the FPGA side. Indeed, when a lose occurs, this lose is not detected in the FPGA. All the sequence of data leave the FPGA correctly. 

 

So, the problem can come from the fact that the FT2232H chip tells that he can receive a byte (his fifo is not full) but this is not true in this case I dont know how to resolve this. But the problem can come from somewhere else.
Altera_Forum
Honored Contributor I
63 Views

It could still be a timing problem. Do you need to set any input/output delays on your IOs to compensate for trace delays?

Altera_Forum
Honored Contributor I
63 Views

What OS are you using on the PC side?

Altera_Forum
Honored Contributor I
63 Views

 

--- Quote Start ---  

What OS are you using on the PC side? 

--- Quote End ---  

 

 

Windows seven 64bits
Altera_Forum
Honored Contributor I
63 Views

OK, I once (years ago) had a problem with the Linux driver for this part. I've successfully used the part with Win7-46bit. Nevertheless one thing you could try is monitoring, RXF#, TXF#, RD#, WR# with a high speed scope for glitches. This is not an easy measurement as the glitch, if one exists, will be very low duty cycle.

Altera_Forum
Honored Contributor I
63 Views

Do you monitor RXF on falling edge of clock? 

 

See  

 

http://electro-logic.blogspot.it/2014/03/fpga-comunicazione-ad-alta-velocita_1.html 

 

And let us know 

 

 

--- Quote Start ---  

Dear All, 

 

I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the sent data to PC. 

 

 

I am using the 245 fifo sync mode. 

 

All is working fine, expect that I rarely have a lose of one byte that appears randomly. 

 

So for example, when I send a packet of 512byte, i received well the 512byte but when I repeat this operations 200 times, I noticed that sometimes I only receive 511 byte and when I check where happens the lost byte, it happens randomly. And when I send a packet of 65.536 byte, again sometimes, I only received 65 535 byte. 

 

The strange thing is that when a lose occurs, this is always one byte. 

 

Can anyone help out me there to solve this problem ? 

 

Attached you will find my VHDL code. 

 

Thank you for your help ! 

--- Quote End ---  

Altera_Forum
Honored Contributor I
63 Views

I believe what I saw (years ago) was a situation in which RXF (or TXF) was in a high state, then it momentarily glitched low when it should have remained high. This created problems with the state machine in the FPGA.

Altera_Forum
Honored Contributor I
63 Views

 

--- Quote Start ---  

I believe what I saw (years ago) was a situation in which RXF (or TXF) was in a high state, then it momentarily glitched low when it should have remained high. This created problems with the state machine in the FPGA. 

--- Quote End ---  

 

 

This would indicate a timing or design problem. Glitches would not be getting to your sm logic. This would imply poor synchronisation.
Altera_Forum
Honored Contributor I
63 Views

The "poor synchronization" was on the part of the FT2232 chip/driver, since it supplies RXF, TXF and the clock. These signals are supposed to be synchronous but they were not. As I mentioned, the Windows driver worked fine, the Linux driver showed the glitch.

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