Hello,
I am implementing a multi-lane Interlaken PHY design on a Stratix V part. There seems to be a dearth of documentation and experience regarding this IP. Specifically, I see some strange behaviors on my TX logic. I have location-constrained my PLLs (3 of them to support 16 lanes of TX) to reliably achieve PLL_LOCK. However, my success with TX_SYNC_DONE seems to vary arbitrarily from compile to compile. If I have the PLLs location-locked and have my REF_CLK defined at 156.25 MHz, under what scenario would I achieve PLL_LOCK but not TX_SYNC_DONE? Are there additional constraints that I should be aware of?
Similarly, what constraints are needed for the RX portion of the Interlaken PHY? Do I need to account for jitter on recovered clocks that I use to drive the user side of the RX interface?
Any help on Interlaken PHY, or Altera transceivers in general, would be much appreciated!!!
Regards,
romno
