Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Honored Contributor I
714 Views

Issues with Interlaken PHY on Stratix V

Hello, 

 

I am implementing a multi-lane Interlaken PHY design on a Stratix V part. There seems to be a dearth of documentation and experience regarding this IP. Specifically, I see some strange behaviors on my TX logic. I have location-constrained my PLLs (3 of them to support 16 lanes of TX) to reliably achieve PLL_LOCK. However, my success with TX_SYNC_DONE seems to vary arbitrarily from compile to compile. If I have the PLLs location-locked and have my REF_CLK defined at 156.25 MHz, under what scenario would I achieve PLL_LOCK but not TX_SYNC_DONE? Are there additional constraints that I should be aware of? 

 

Similarly, what constraints are needed for the RX portion of the Interlaken PHY? Do I need to account for jitter on recovered clocks that I use to drive the user side of the RX interface? 

 

Any help on Interlaken PHY, or Altera transceivers in general, would be much appreciated!!! 

 

Regards, 

 

romno
0 Kudos
1 Reply
Highlighted
Honored Contributor I
5 Views

Romno, 

 

Hi, did you every solve your problems with Interlaken? Also, are you using NIOS in your design? If you solved your problems would you recommend others to use the Interlaken IP?  

Thanks, joe
0 Kudos