JESD IP settings and RX Interrupt Access

[WGith]

Hi,

We are using the JESD IP core in the following confirguartions

LMF: 812 & 412. We have this working with no problems.

We recently tried to change to using LMF: 822 as we are interfacing with a dual ADC part and wanted to sample the other channel as well.

I changed the IP core to M=2 and I also changed from S=8 to S=4 as that was what the AN832 says is a valid configuration. I build the image and during testing I get the following results.

RX_ISLOCKED_DATA (0xff), BUT data_align = '0', not the typically '1' I expect.

The other difference I get is that RX_INTERRUPT = '1', versus the normal '0'. Now I have made sure that the configu and status register block is checked and I have tired accessing the 0x60 and 0x64 registers to see what is causing the error, but no matter what I do, I can not seem to get a response from the JESD IP AVS bus. I have read the Avalon-mm interface document and believe I am doing everything correct to get a response.

So, Im trying to figure out if I just have a setting incorrect in the LMF selections, and / or how to interface with the config/status registers so I can determine what the exactly error is even though I am locked to the data.

Thank you,

Will

[Nathan_R_Intel]

Will, Since you are using AN832, I believe you are using Stratix 10 device. Could you confirm you are using Stratix 10. Being locked-to-data only indicates that your Receiver is receiving data at the desired frequency (or data rate). It does not mean you are receiving the correct data in the timing order that is required. Please refer to JESD IP user guide (section 4.2.1 onwards) on what type of data you should be receiving to transition to different phases from CGS to ILAS to user mode. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf Please check by probing the mentioned signals using signaltap to help resolves your data_align = 0 issue. If you need further help related to debugging the data_align issue, please capture the following status signals in signaltap and attach the .stp file. -jesd204_rx_dataout -jesd204_rx_data_valid -jesd204_rx_data_ready -jesd204_rx_link_data_ready -jesd204_rx_link_error - rx_dev_sync_n - jesd204_rx_int - dev_lane_aligned - rx_somf -jesd204_rx_pcs_data -jesd204_rx_pcs_data_valid -jesd204_rx_pcs_kchar_data -jesd204_rx_pcs_errdetect -jesd204_rx_pcs_disperr Since you are using a supported LMF configuration, I am not suspecting your issue to be caused by changing the LMF configuration. As for the RX_INTERRUPT = 1, please check your AVS related clock frequency and the reset as described in section 4.5 of the user guide. Please let me know if you checked everything listed above and still cannot zoom in. Also, it will be halpful it you could attach signaltap snapshots on FPGA or register readback in system console showing the failures reported. This will enable me to more effectively help you debug your issue. Regards, Nathan

[WGith]

Nathan, Thank you for your detailed writeup. It was very helpful. I have not had a lot of time to make much progress, but signaltap does show that dev_sync_n is toggling so there is something going on in the initialization handshaking. I will get back to you hopefully more tomorrow, but wanted to let you know my small update and thank you for your help. --Will

[WGith]

Nathan,

I was able to get the design working! I decided to regenerate the JESD IP from scratch and inputted all the parameters as expected. I also made sure to use the latest version of quartus 18.1.2 Build 277. This worked, so I am sticking with it!

Thank you for your help.

--Will

[Nathan_R_Intel]

Ok. Good to know you have got your design working. Regards, Nathan