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JESD204B DEV_SYNC_N, Rx Link Up is LOW and dev_aligned is LOW

  1. I have Arrira 10 SoC (p/n = 10AS066N2F40E2SG) on my new board.
  2. I have 8 lanes JESD204B Rx connected to ADC12DJ3200.
  3. I got signal tap for debug

 

So far,

1) - I got rx_is_lockedtodata[7:0] are HIGH with x"BCBCBC..." received on jesd204_rx_pcs_data (renamed to serdes_data_in) with jesd204_rx_pcs_data_valid is HIGH.

 

2) However the dev_sync_n stays in LOW so that the ADC won't send data to FPGA (jesd204).

 

3) attached is a screenshot on some of buses.

 

I would like to get your insights and suggestions. Thanks.

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1 Reply
Nathan_R_Intel
Employee
88 Views

Hie,

 

Your signaltap is missing some critical signals such as sync_n; hence its difficult to make a concludion on what is going on.

Please add signal following Figure 33 of the user guide and refer to the description of the timing diagram to understand whats going wrong in your system.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf

 

Please check that and let me know if you have further questions.

 

Regards,

Nathan

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