JESD204B TX ipcore使用问题！

[圣叶000]

最近在评估A10与ADI AD9161间204B接口时，硬件工作在JESD204B subclass0，Lane rate=12.5Gbps，实际评估时发现如下问题，请问我该如何排查问题。ipcore的jesd204_tx_int型号拉高，我查询到ipcore寄存器地址0x60=8'h11,0x80=8'h01,0x54=8'h05,通过寄存器网页：https://www.altera.com/support/literature/ug/altera_jesd204_tx_regmap.html 中对应3个寄存器功能解释说明，通过根据https://www.intel.cn/content/www/cn/zh/programmable/documentation/bhc1411117158599.html JESD204B Intel FPGA IP User Guide中第4.3.4. Link Reinitialization （P60页）的描述，我还是不清楚我该怎样对整个jesd204b link进行Reinitialization，能否提供更详细的Reinitialization流程? 另外JESD204B Intel FPGA IP User Guide中第61页有如下的描述：Hardware initiated link reinitialization can be globally disabled through the csr_link_reinit_disable register for debug purposes.但是我在altera_jesd204_tx_regmap.html 中没有找到csr_link_reinit_disable register的说明，只有地址为0x54的bit0是csr_link_reinit。从字面意思不是Hardware initiated link reinitialization的功能，这个地方是我理解错了吗？Hardware initiated link reinitialization功能我该如何实现呢？

[Nathan_R_Intel]

Hie, I translated your description in mandarin as following: Recently, when evaluating the 204B interface between A10 and ADI AD9161, the hardware works in JESD204B subclass0, Lane rate=12.5Gbps. The following problems are found during the actual evaluation. How can I troubleshoot the problem? Ipcore's jesd204_tx_int model is pulled high, I query the ipcore register address 0x60=8'h11, 0x80=8'h01, 0x54=8'h05, through the register page: https://www.altera.com/support/literature/ug /altera_jesd204_tx_regmap.html The corresponding three register function explanations are explained in accordance with https://www.intel.cn/content/www/cn/en/programmable/documentation/bhc1411117158599.html JESD204B Intel FPGA IP User Guide, Section 4.3. 4. The description of Link Reinitialization (page 60), I still don't know how to reinitialize the entire jesd204b link, can I provide a more detailed Reinitialization process? In addition, the JESD204B Intel FPGA IP User Guide page 61 has the following description: Hardware initiated link reinitialization can be globally disabled through the csr_link_reinit_disable register for debug purposes. But I did not find the description of csr_link_reinit_disable register in altera_jesd204_tx_regmap.html, only bit 0 with address 0x54 is csr_link_reinit. The literal meaning is not the function of Hardware initiated link reinitialization. Is this place I understand wrong? How should I implement the Hardware initiated link reinitialization function? Www.altera.com Https://www.altera.com/support/literature/ug/altera_jesd204_tx_regmap.html Please check my replies to your questions: 1. The following problems are found during the actual evaluation. How can I troubleshoot the problem? Ipcore's jesd204_tx_int model is pulled high jesd204_tx_int is the interrupt pin for JESD204B IP core. Interrupt is asserted when there is an error or sync is detected. As described in Table 23, Pg 84 (of JESD204B user guide), please configure tx_err_enable register to identify the type of error. https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf You will need to disable the register bits by setting 0 to disable the specific error type from generating the interrupt. Please let me know the type of error for further debug. I can provide my analysis and make recommendation based on this. https://www.intel.com/content/www/us/en/programmable/support/literature/ug/altera_jesd204_tx_regmap.html Another method is by observing the status signals in signaltap and system console to identify the issue. Please refer to section 6.7 on debugging JESD204B link using system console from the JESD204B user guide. 2. I still don't know how to reinitialize the entire jesd204b link, can I provide a more detailed Reinitialization process? The Pg61 only describes the supported link re-initialization mode which is hardware and software for both Tx and Rx. This page does not provide the method how to trigger hardware link re-initialization. I will describe below (in Question 4) on how to trigger link re-initialization. 3. But I did not find the description of csr_link_reinit_disable register in altera_jesd204_tx_regmap.html, only bit 0 with address 0x54 is csr_link_reinit. The literal meaning is not the function of Hardware initiated link reinitialization. Is this place I understand wrong? Yes the csr_link_reinit_disable is not meant to trigger link re-initialization. This CSR bit is only meant to disable the hardware link re-initialization capability for debugging purpose. 4. How should I implement the Hardware initiated link re-initialization function? Hardware link re-initialization can only be issued as an interrupt when error occurs depending on error type. Hardware link re-initialization is automatic and cannot be triggered using CSR register write. Software initiated link re-initialization is supported by both Tx and Rx IP core. The software can request link re-initialization as following: i. For TX, the software initiate IP core to transmits /K/ character. This re-trigger link re-initialization. ii. For RX, the software initiate IP core to assert SYNC_N to request for link re-initialization. Regards, Nathan